This disclosure describes various examples of a system which uses a multi-bank, multi-port
shared memory system that may be implemented as part of a system on a chip. The shared …

2020-07-06 Assigned to FACEBOOK TECHNOLOGIES, LLC reassignment FACEBOOK
TECHNOLOGIES, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

This disclosure describes system on a chip (SOC) commu nications that prevent direct
memory access (DMA) attacks. An example SoC includes an encryption engine and a …

A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to
split a phase of a reference clock signal to output a first reference clock signal and a second …

Abstract Changes in a clock signal, such as phase changes or resets, may propagate
glitches, such as shortened clock cycles that may cause undesired effects in subsequent …

Clock alignment circuitry may include phase detection circuitry and programmable delay
circuitry to facilitate aligning a data signal with a particular state of a clock signal. For …

This disclosure describes system on a chip (SOC) communications that prevent direct
memory access (DMA) attacks. An example SoC includes an encryption engine and a …

This disclosure describes various examples of a system which uses a multi-bank, multi-port
shared memory system that may be implemented as part of a system on a chip. The shared …

the synchronization circuit is configured to perform a synchronization operation to convert a
first control signal in a first clock domain into a second control signal in a second clock …

This disclosure describes techniques that include aligning processing of audio samples
collected by multiple audio sensors or microphones. In one example, this disclosure …