Hardware implementation of MPI_Barrier on an FPGA cluster
S Gao, AG Schmidt, R Sass - 2009 International Conference on …, 2009 - ieeexplore.ieee.org
Message-Passing is the dominant programming model for distributed memory parallel
computers and Message-Passing Interface (MPI) is the standard. Along with point-to-point …
computers and Message-Passing Interface (MPI) is the standard. Along with point-to-point …
AIREN: A novel integration of on-chip and off-chip FPGA networks
AG Schmidt, WV Kritikos, RR Sharma… - 2009 17th IEEE …, 2009 - ieeexplore.ieee.org
The Reconfigurable Computing Cluster Project at the University of North Carolina at
Charlotte is investigating the feasibility of using FPGAs as compute nodes to scale to …
Charlotte is investigating the feasibility of using FPGAs as compute nodes to scale to …
The challenges of using an embedded MPI for hardware-based processing nodes
DL Ly, M Saldana, P Chow - 2009 International Conference on …, 2009 - ieeexplore.ieee.org
This paper presents several challenges and solutions in designing an efficient Message
Passing Interface (MPI) implementation for embedded FPGA applications. Popular MPI …
Passing Interface (MPI) implementation for embedded FPGA applications. Popular MPI …
An evaluation of an integrated on‐chip/off‐chip network for high‐performance reconfigurable computing
AG Schmidt, WV Kritikos, S Gao… - International Journal of …, 2012 - Wiley Online Library
As the number of cores per discrete integrated circuit (IC) device grows, the importance of
the network on chip (NoC) increases. However, the body of research in this area has …
the network on chip (NoC) increases. However, the body of research in this area has …
Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster
AG Schmidt, S Datta, AA Mendon, R Sass - Parallel Computing, 2012 - Elsevier
The Reconfigurable Computing Cluster project is exploring novel parallel computing
architectures in high performance computing with FPGA devices. Although there are no …
architectures in high performance computing with FPGA devices. Although there are no …
A hardware filesystem implementation with multidisk support
AA Mendon, AG Schmidt, R Sass - International Journal of …, 2009 - Wiley Online Library
Modern High‐End Computing systems frequently include FPGAs as compute accelerators.
These programmable logic devices now support disk controller IP cores which offer the …
These programmable logic devices now support disk controller IP cores which offer the …
Genetic algorithm for Boolean minimization in an FPGA cluster
Evolutionary algorithms are an alternative option to the Boolean synthesis due to that they
allow one to create hardware structures that would not be able to be obtained with other …
allow one to create hardware structures that would not be able to be obtained with other …
Implementation of search process for a content-based image retrieval application on system on chip
R Molina, FR Calle, JD Gazzano… - 2019 X Southern …, 2019 - ieeexplore.ieee.org
The amount of multimedia information on digital platforms has been increasing over the
years. Social networks and the advancement of technology have been a determining factor …
years. Social networks and the advancement of technology have been a determining factor …
Síntesis booleana con programación genética paralela en CPU y GPU
La síntesis booleana o combinacional es un proceso mediante el cual se optimiza una red
de puertas lógicas, con el fin de reducir su consumo, minimizar costos, minimizar área y …
de puertas lógicas, con el fin de reducir su consumo, minimizar costos, minimizar área y …
Parallel algorithm for evolvable-based boolean synthesis on GPUs
The use of evolutionary algorithms in the boolean synthesis is an attractive alternative to
generate interesting and efficient hardware structures, with a high computational load. This …
generate interesting and efficient hardware structures, with a high computational load. This …