MachSuite: Benchmarks for accelerator design and customized architectures

B Reagen, R Adolf, YS Shao, GY Wei… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
Recent high-level synthesis and accelerator-related architecture papers show a great
disparity in workload selection. To improve standardization within the accelerator research …

OpenCL-based FPGA-platform for stencil computation and its optimization methodology

HM Waidyasooriya, Y Takei, S Tatsumi… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Stencil computation is widely used in scientific computations and many accelerators based
on multicore CPUs and GPUs have been proposed. Stencil computation has a small …

An initial exploration of a multi-sensory design space: Tactile support for walking in immersive virtual environments

M Feng, A Dey, RW Lindeman - 2016 IEEE symposium on 3D …, 2016 - ieeexplore.ieee.org
Multi-sensory feedback can potentially improve user experience and performance in virtual
environments. As it is complicated to study the effect of multi-sensory feedback as a single …

An optimal microarchitecture for stencil computation acceleration based on non-uniform partitioning of data reuse buffers

J Cong, P Li, B Xiao, P Zhang - Proceedings of the 51st annual design …, 2014 - dl.acm.org
High-level synthesis (HLS) tools have made significant progress in compiling high-level
descriptions of computation into highly pipelined register-transfer level (RTL) specifications …

On how to accelerate iterative stencil loops: a scalable streaming-based approach

R Cattaneo, G Natale, C Sicignano, D Sciuto… - ACM Transactions on …, 2015 - dl.acm.org
In high-performance systems, stencil computations play a crucial role as they appear in a
variety of different fields of application, ranging from partial differential equation solving, to …

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

G Natale, G Stramondo, P Bressana… - 2016 IEEE/ACM …, 2016 - ieeexplore.ieee.org
Iterative Stencil Loops (ISLs) are a specific class of algorithms of great importance for their
substantial presence in a lot of industrial and scientific computing applications, such as in …

[PDF][PDF] High performance computing with FPGAs and OpenCL

HR Zohouri - arXiv preprint arXiv:1810.09773, 2018 - t2r2.star.titech.ac.jp
With the impending death of Moore's law, the High Performance Computing (HPC)
community is actively exploring new options to satisfy the never-ending need for faster and …

A comprehensive framework for synthesizing stencil algorithms on FPGAs using OpenCL model

S Wang, Y Liang - Proceedings of the 54th Annual Design Automation …, 2017 - dl.acm.org
Iterative stencil algorithms find applications in a wide range of domains. FPGAs have long
been adopted for computation acceleration due to its advantages of dedicated hardware …

An exploration framework for efficient high-level synthesis of support vector machines: Case study on ecg arrhythmia detection for xilinx zynq soc

V Tsoutsouras, K Koliogeorgi, S Xydis… - Journal of Signal …, 2017 - Springer
Abstract In recent years, Support Vector Machine (SVM) classifiers have played a crucial
role in providing data fusion and high accuracy classification solutions for various, complex …

DCMI: A scalable strategy for accelerating iterative stencil loops on FPGAs

M Koraei, O Fatemi, M Jahre - ACM Transactions on Architecture and …, 2019 - dl.acm.org
Iterative Stencil Loops (ISLs) are the key kernel within a range of compute-intensive
applications. To accelerate ISLs with Field Programmable Gate Arrays, it is critical to exploit …