Abstract Three-dimensional (3D) integration is considered an effective approach to extend
and expand Moore's Law. Among them, Through-Silicon Via (TSV) technology provides …

Abstract Three-dimensional (3D) integrated packaging technology is gradually moving from
the laboratory to the market. Through silicon via (TSV) is the most critical structural unit in 3D …

Copper filled through silicon via (TSV-Cu) is a crucial technology for chip stacking and three-
dimensional (3D) vertical packaging. The multiple thermal loadings caused by the annealing …

Thermomechanical reliability remains challenging in through-silicon via (TSV) manufacture,
a key technology in three-dimensional packaging of integrated circuits. A primary issue in …

In this paper, the residual stresses with a nanoscale depth resolution at TSV-Cu/TiW/SiO2/Si
interfaces under different thermal loadings are characterized using the ion-beam layer …

Mitigation of the degradation for down-scaled interconnects requires an in-depth
understanding of the failure mechanisms of electromigration and, therefore, the …

Annealing process is generally adopted to reduce the residual stress and stabilize the
microstructure of TSV-Cu in IC manufacturing. In this paper, the effects of capped Cu layer …

Abstract Through‑silicon-via (TSV) microstructure is the key structure of 3D integrated
packaging, and its reliability during service plays a very important role in the long-term …

Herein, annealing experiments were performed on Cu-filled through silicon via (Cu-TSV)
samples in the temperature range of 250–550° C and the relevant microstructural aspects …

With the development of 3D integrated packaging technology, failure analysis is facing more
and more challenges. Defect localization in a 3D package is a key step of failure analysis …