Digital circuit design challenges and opportunities in the era of nanoscale CMOS
Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
A survey of architectural techniques for managing process variation
S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …
slow down and even pause technological scaling, and mitigation of it is the way to continue …
McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures
This paper introduces McPAT, an integrated power, area, and timing modeling framework
that supports comprehensive design space exploration for multicore and manycore …
that supports comprehensive design space exploration for multicore and manycore …
The future of microprocessors
The future of microprocessors Page 1 MAy 2011 | vOl. 54 | nO. 5 | CommunICatIons of the aCm
67 MICroProCessors—sInGLe-ChIP CoMPUters—are the building blocks of the information …
67 MICroProCessors—sInGLe-ChIP CoMPUters—are the building blocks of the information …
Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits
RG Dreslinski, M Wieckowski, D Blaauw… - Proceedings of the …, 2010 - ieeexplore.ieee.org
Power has become the primary design constraint for chip designers today. While Moore's
law continues to provide additional transistors, power budgets have begun to prohibit those …
law continues to provide additional transistors, power budgets have begun to prohibit those …
A robust and energy-efficient classifier using brain-inspired hyperdimensional computing
The mathematical properties of high-dimensional (HD) spaces show remarkable agreement
with behaviors controlled by the brain. Computing with HD vectors, referred to as" …
with behaviors controlled by the brain. Computing with HD vectors, referred to as" …
Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
S Borkar - Ieee Micro, 2005 - ieeexplore.ieee.org
As technology scales, variability in transistor performance continues to increase, making
transistors less and less reliable. This creates several challenges in building reliable …
transistors less and less reliable. This creates several challenges in building reliable …
Thousand core chips: a technology perspective
S Borkar - Proceedings of the 44th annual design automation …, 2007 - dl.acm.org
This paper presents the many-core architecture, with hundreds to thousands of small cores,
to deliver unprecedented compute performance in an affordable power envelope. We …
to deliver unprecedented compute performance in an affordable power envelope. We …
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-
volatile resistive memories are being developed as a potential replacement. Unfortunately …
volatile resistive memories are being developed as a potential replacement. Unfortunately …
Hardware Trojan detection by multiple-parameter side-channel analysis
S Narasimhan, D Du, RS Chakraborty… - IEEE Transactions …, 2012 - ieeexplore.ieee.org
Hardware Trojan attack in the form of malicious modification of a design has emerged as a
major security threat. Sidechannel analysis has been investigated as an alternative to …
major security threat. Sidechannel analysis has been investigated as an alternative to …