With increasing time-to-market pressure and shortening semiconductor product cycles, more
and more chips are being designed with library-based methodologies. In spite of this shift …

In this paper we survey major problems faced by EDA tools in tackling deep submicron
(DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay …

We consider the problem of choosing the gate sizes or scale factors in a combinational logic
circuit in order to minimize the total area, subject to simple RC timing constraints, and a …

It has been demonstrated by Serre et al. that the biologically inspired model (BIM) is effective
for object recognition. It outperforms many state-of-the-art methods in challenging …

The effectiveness of logic synthesis to satisfy increasingly tight timing constraints in deep-
submicron high-performance circuits heavily depends on the range and variety of logic …

A physical design flow consists of producing a production-worthy layout from a gate-level
netlist subject to a set of constraints. This paper focuses on the problems imposed by …

Novel methodology and algorithms to seamlessly integrate logic synthesis and physical
placement through a transformational approach are presented. Contrary to most placement …

The wavefront technology mapping algorithm leads to a very simple and efficient
implementation that elegantly decouples pattern matching and covering but circumvents that …

We propose a timing-driven discrete cell-sizing algorithm that can incorporate total cell size
constraints. We model cell sizing as a min-cost network flow problem. In the network flow …

A Web site is a semi structured collection of different kinds of data, whose motivation is to
show relevant information to a visitor and in this way capture her/his attention …