A survey of machine learning for computer architecture and systems
It has been a long time that computer architecture and systems are optimized for efficient
execution of machine learning (ML) models. Now, it is time to reconsider the relationship …
execution of machine learning (ML) models. Now, it is time to reconsider the relationship …
Accurate operation delay prediction for FPGA HLS using graph neural networks
Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for
boosting the performance of arithmetic-intensive designs, such as DSP blocks and carry …
boosting the performance of arithmetic-intensive designs, such as DSP blocks and carry …
IronMan-Pro: Multiobjective design space exploration in HLS via reinforcement learning and graph neural network-based modeling
Despite the great success of high-level synthesis (HLS) tools, we observe several
unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes …
unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes …
High-level power estimation techniques in embedded systems hardware: an overview
Power optimization has become a major concern for most digital hardware designers,
particularly in early design phases and especially in limited power budget systems (battery …
particularly in early design phases and especially in limited power budget systems (battery …
High-level synthesis hardware design for fpga-based accelerators: Models, methodologies, and frameworks
Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …
(SoC) devices have gained attention in recent years. One of the main reasons is that these …
Transfer learning for design-space exploration with high-level synthesis
J Kwon, LP Carloni - Proceedings of the 2020 ACM/IEEE Workshop on …, 2020 - dl.acm.org
High-level synthesis (HLS) raises the level of design abstraction, expedites the process of
hardware design, and enriches the set of final designs by automatically translating a …
hardware design, and enriches the set of final designs by automatically translating a …
Powergear: Early-stage power estimation in FPGA HLS via heterogeneous edge-centric GNNs
Power estimation is the basis of many hardware optimization strategies. However, it is still
challenging to offer accurate power estimation at an early stage such as high-level synthesis …
challenging to offer accurate power estimation at an early stage such as high-level synthesis …
HLSDataset: Open-source dataset for ML-assisted FPGA design using high level synthesis
Machine Learning (ML) has been widely adopted in design exploration using high level
synthesis (HLS) for faster resource, timing and power estimation at very early stages for …
synthesis (HLS) for faster resource, timing and power estimation at very early stages for …
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators
Parameterizable machine learning (ML) accelerators are the product of recent
breakthroughs in ML. To fully enable their design space exploration (DSE), we propose a …
breakthroughs in ML. To fully enable their design space exploration (DSE), we propose a …
Application of Machine Learning in FPGA EDA Tool Development
With the recent advances in hardware technologies like advanced CPUs and GPUs and the
large availability of open-source libraries, machine learning has penetrated various …
large availability of open-source libraries, machine learning has penetrated various …