A survey on FEC techniques for industrial wireless communications
Industry 4.0 aims to digitize industrial processes entirely, and wireless technologies
represent one of the enablers for scalable and flexible communications. However, the …
represent one of the enablers for scalable and flexible communications. However, the …
A 640-Mb/s 2048-bit programmable LDPC decoder chip
MM Mansour, NR Shanbhag - IEEE Journal of Solid-State …, 2006 - ieeexplore.ieee.org
A 14.3-mm/sup 2/code-programmable and code-rate tunable decoder chip for 2048-bit low-
density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding …
density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding …
Low density parity check decoder for regular LDPC codes
KK Gunnam - US Patent 8,359,522, 2013 - Google Patents
613371642 B1 V2002 Yaoilleta' 2003/0081693 A1 5/2003 Raghaven etal. 1 1 g.
2003/0087634 A1 5/2003 Raghaven et a1. 613511832 B1 2/2002 We ' 2003/0112896 A1 …
2003/0087634 A1 5/2003 Raghaven et a1. 613511832 B1 2/2002 We ' 2003/0112896 A1 …
Low density parity check decoder for irregular LDPC codes
KK Gunnam - US Patent 8,418,023, 2013 - Google Patents
US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents
US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents …
US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents …
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
Y Sun, JR Cavallaro - Integration, 2011 - Elsevier
We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by
utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) …
utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) …
Parallel interleaver design for a high throughput HSPA+/LTE multi-standard turbo decoder
To meet the evolving data rate requirements of emerging wireless communication
technologies, many parallel architectures have been proposed to implement high …
technologies, many parallel architectures have been proposed to implement high …
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless
systems. To support various 4G standards, a configurable multi-mode MAP (maximum a …
systems. To support various 4G standards, a configurable multi-mode MAP (maximum a …
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
Standard VLSI implementations of turbo decoding require substantial memory and incur a
long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for …
long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for …
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
Iterative decoding of convolutional turbo code (CTC) has a large memory power
consumption. To reduce the power consumption of the state metrics cache (SMC), low …
consumption. To reduce the power consumption of the state metrics cache (SMC), low …
A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system
CC Wong, YY Lee, HC Chang - 2009 Symposium on VLSI …, 2009 - ieeexplore.ieee.org
This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE
standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block …
standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block …