Cell circuit and layout with linear finfet structures
ST Becker - US Patent 9,563,733, 2017 - Google Patents
(57) ABSTRACT A cell circuit and corresponding layout is disclosed to include linear-
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
Finfet transistor circuit
ST Becker, MC Smayling, D Gandhi, J Mali… - US Patent …, 2014 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Dynamic array architecture
ST Becker, MC Smayling - US Patent 7,446,352, 2008 - Google Patents
5,923,059 A 7/1999 Gheewala................... 257/204 of the substrate. The semiconductor
device includes a number of linear gate electrode tracks de? ned to extend over the …
device includes a number of linear gate electrode tracks de? ned to extend over the …
Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
ST Becker, MC Smayling - US Patent 7,888,705, 2011 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Semiconductor device with dynamic array section
ST Becker, MC Smayling - US Patent 7,917,879, 2011 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Methods for defining contact grid in dynamic array architecture
J Hong, S Kornachuk, ST Becker - US Patent 8,225,261, 2012 - Google Patents
First and second virtual grates are defined as respective sets of parallel virtual lines
extending across a layout area in first and second perpendicular directions, respectively …
extending across a layout area in first and second perpendicular directions, respectively …
Methods for designing semiconductor device with dynamic array section
ST Becker, MC Smayling - US Patent 7,908,578, 2011 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Simultaneous source mask optimization (SMO)
R Socha, X Shi, D LeHoty - Photomask and Next-Generation …, 2005 - spiedigitallibrary.org
In this paper, a method for improving the process window is described by simultaneous
source mask optimization (SMO). The method optimizes the source and mask of a critical …
source mask optimization (SMO). The method optimizes the source and mask of a critical …
Cross-coupled transistor layouts in restricted gate level layout architecture
ST Becker - US Patent 7,956,421, 2011 - Google Patents
5497334 A 3/1996 Russell “. 31 6,633,182 B2 10/2003 Pileggi et a1. 5,497,337 A 3/1996
Ponnapalh et a1. 6 643 831 B2 110003 Chang et a1 '5,581,098 A 12/1996 Chang …
Ponnapalh et a1. 6 643 831 B2 110003 Chang et a1 '5,581,098 A 12/1996 Chang …
Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
ST Becker, MC Smayling - US Patent 8,283,701, 2012 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …