A vector-length agnostic compiler for the connex-s accelerator with scratchpad memory
AE Şuşu - ACM Transactions on Embedded Computing Systems …, 2020 - dl.acm.org
Compiling sequential C programs for Connex-S, a competitive, scalable and customizable,
wide vector accelerator for intensive embedded applications with 32 to 4,096 16-bit integer …
wide vector accelerator for intensive embedded applications with 32 to 4,096 16-bit integer …
Extending clang/LLVM with custom instructions using TableGen–an experience report
J Schlamelcher, T Goodfellow… - MBMV 2024; 27 …, 2024 - ieeexplore.ieee.org
The extensibility of the RISC-V ISA by adding instructions allows for the rapid creation of
custom processor cores. For that reason, it must be assured that the software tooling for this …
custom processor cores. For that reason, it must be assured that the software tooling for this …
[HTML][HTML] Towards a Dynabook for verified VM construction
B Shingarov, J Vraný - Journal of Computer Languages, 2024 - Elsevier
We present Smalltalk-25, a scientific Programm of research towards the synthesis of
Smalltalk VMs by formal methods. We approach this through a Dynabook-style …
Smalltalk VMs by formal methods. We approach this through a Dynabook-style …
Live proof-by-induction
BG Shingarov - FAST Workshop 2022 on Smalltalk Related …, 2022 - openreview.net
Refinement types are a powerful formalism with many applications in program verification,
compiler optimization, etc. We present our work-in-progress on MachineArithmetic, an …
compiler optimization, etc. We present our work-in-progress on MachineArithmetic, an …
[PDF][PDF] Formal verification of JIT by symbolic execution
B Shingarov - International Workshop on Virtual Machines and …, 2019 - shingarov.com
This work-in-progress report presents ongoing experiments relating to formal verification of
JIT compilers for language VMs. The native CPU code of the VM—which consists of …
JIT compilers for language VMs. The native CPU code of the VM—which consists of …
An automatic energy consumption characterization of processors using ArchC
The design complexity of integrated circuits requires techniques that automate and ease
common tasks, allowing developers to keep up with the rapid growth and demand of the …
common tasks, allowing developers to keep up with the rapid growth and demand of the …
Live introspection of target-agnostic JIT in simulation
B Shingarov - Proceedings of the International Workshop on …, 2015 - dl.acm.org
Proceedings of the International Workshop on Smalltalk Technologies: Live Introspection of
Target-Agnostic JIT in Simulation Page 1 Live Introspection of Target-Agnostic JIT in Simulation …
Target-Agnostic JIT in Simulation Page 1 Live Introspection of Target-Agnostic JIT in Simulation …
Architecture description language based retargetable symbolic execution
A Ibing - 2015 Design, Automation & Test in Europe …, 2015 - ieeexplore.ieee.org
This paper presents an approach to retargetable SMT-constrained symbolic execution of
machine code. The retargetability is based on an existing open-source processor …
machine code. The retargetability is based on an existing open-source processor …
Programming a Smalltalk VM in Coq
B Shingarov - Proceedings of the 12th edition of the International …, 2017 - dl.acm.org
We describe an experimental attempt at verification of Smalltalk VM using mechanized
proof. Only the native code generation part is verified. The generator is developed in the …
proof. Only the native code generation part is verified. The generator is developed in the …
[PDF][PDF] Modern Problems for the Smalltalk VM
B Shingarov - … Workshop on Smalltalk Technologies, Cambridge, UK, 2014 - shingarov.com
I propose an approach to managing new classes of Smalltalk VM complexity which emerged
due to recent advances in technology, through the execution of the VM on formal models of …
due to recent advances in technology, through the execution of the VM on formal models of …