A third-order continuous-time multibit (4 bit)/spl Delta//spl Sigma/ADC for wireless
applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power …

Continuous-time ΔΣ modulators used in wireless transceivers need to digitize small desired
signals that are accompanied by large out-of-band interferers. In such applications, it is …

(57) ABSTRACT A continuous-time sigma-delta analog-to-digital converter (CV) including i)
a signal path (SP) having at least one com biner (C1) for combining analog signals to …

A continuous-time 4th-order multi-bit/spl Sigma//spl Delta/-modulator for GSM/EDGE is
presented. By introduction of a direct feed-forward path from the input to the quantiser, high …

This work analyzes the performance evolution over time for monolithic A/D-Converter (ADC)
implementations reported in scientific publications. The work is based on an exhaustive …

As the miniaturization of semiconductor technology continues, electronic s-tems on chips o?
er a more extensive and more complex functionality with better performance, higher …

This work presents a general method to design continuous-time/spl Sigma//spl
Delta/modulators with sine-shaped feedback DACs. A discrete time to continuous time …

The high dynamic range of CTΔΣMs used in wireless receivers, needed to accommodate
large out-of-band interferers, can be reduced by using a filter up front. Embedding the filter …

A parallel multibit continuous-time (CT) ΔΣ analog-to-digital converter for an orthogonal-
frequency-division-multiplexing (OFDM) ultrawideband receiver intended to operate …

The present application claims priority to US Provisional Patent Application No. 60/636,501
entitled “Mismatch Can cellation in Double Sampling Sigma-Delta ADC, and filed Dec. 16 …