Research of distance-intensity imaging algorithm for pulsed LiDAR based on pulse width correction

S Yan, G Yang, Q Li, Y Wang, C Wang - Remote Sensing, 2022 - mdpi.com
Walking error has been problematic for pulsed LiDAR based on a single threshold
comparator. Traditionally, walk error must be suppressed by some time discrimination …

A fully synthesized injection locked ring oscillator based on a pulse injection locking technique

M Li, RD Mason… - 2017 IEEE Asia Pacific …, 2017 - ieeexplore.ieee.org
This paper proposes a novel, all synthesized, Injection Locked Ring Oscillator (ILRO). It
employs a digitally tunable oscillator and a pulse injection locking technique. The frequency …

Gate driver IC for enhancement mode GaN power transistors with senseFET reverse conduction detection circuit

WJ Zhang, Y Leng, J Yu, X Jiang… - IET Power …, 2019 - Wiley Online Library
Dead‐times are necessary in switching output stage to avoid shoot‐through current between
the high side (HS) and the low side (LS) power transistors. However, excessively long dead …

Appraisal of the Effective Number of Bits of the ADC for Sensors with Account for Dynamic Errors

L Samoilov, D Denisenko… - 2020 IEEE East-West …, 2020 - ieeexplore.ieee.org
The static maximum relative error of the ADC for sensors is determined by the value of its
least significant bit. During the input signal conversion in the ADC the information delay …

A 5.4 ps resolution TDC design with anti-PVT-variation mechanism using 90-nm CMOS process

CC Wang, OLJA Jose, A Avilala - International Journal of …, 2024 - Taylor & Francis
The resolution of time-to-digital converters (TDC) is one parameter that will define its
efficiency. This research demonstrates a 5.4 ps TDC with anti-PVT-variation implemented in …

DESIGN OF A LOW-POWER HIGH-SPEED TRUE SINGLE-PHASE CLOCK D FLIP-FLOP FOR VERNIER TIME-TO-DIGITAL CONVERTERS

LS Kesanasetty, PV Lakshmi… - … and Radio Engineering, 2025 - dl.begellhouse.com
DESIGN OF A LOW-POWER HIGH-SPEED TRUE SINGLE-PHASE CLOCK D FLIP-FLOP
FOR VERNIER TIME-TO-DIGITAL CONVERTERS Page 1 Submitted: 8/31/2023; Accepted …

Time-to-digital converter and digital phase locked loop

H Yan, J Huang, L Lu - US Patent 10,230,383, 2019 - Google Patents
BACKGROUND converting circuits in N stages of converting circuits are different, non-
linearity of output of the time-to-digital con A time-to-digital converter implements conversion …

From algorithm to hardware co-design for multimodal information retrieval of TCSPC data

V Poisson - 2022 - theses.hal.science
Since the invention of the first photon counting sensors, several technological breakthroughs
have been made in the field of photon counting imaging systems, notably with the invention …

A Novel Flash-Type Time-To-Digital Converters (TDC) Using GDI Technique

J Yeshwanth Reddy, A Sushma, S Sravya… - … , Software and Networks …, 2022 - Springer
A proficient flash-type time-to-digital converter is designed by using D flip-flop which is
internally designed by using NAND and NOR gates. The internal architecture of flash-type …

All Digital Phase Locked Loop (ADPLL) and Its Blocks—A Comprehensive Knowledge

L Yadav, M Duhan - International Workshop on New Approaches for …, 2022 - Springer
Abstract The Phase-Locked Loop (PLL) is a feedback system used for the synchronization of
signals in terms of frequency and phase. It is configured in digital communication, Bluetooth …