Modified wallace tree multiplier using efficient square root carry select adder

D Paradhasaradhi, M Prashanthi… - … conference on green …, 2014 - ieeexplore.ieee.org
A multiplier is one of the key hardware blocks in most digital and high performance systems
such as FIR filters, micro processors and digital signal processors etc. A system's …

Fast and area efficient adder for wide data in recent Xilinx FPGAs

P Källström, O Gustafsson - 2016 26th International Conference …, 2016 - ieeexplore.ieee.org
Most modern FPGAs have very optimised carry logic for efficient implementations of ripple
carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof …

[PDF][PDF] An area efficient enhanced SQRT carry select adder

D Paradhasaradhi, K Anusudha - J Eng Res Appl, 2013 - academia.edu
In the design of Integrated Circuits, area occupancy plays a vital role because of increasing
the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders …

Economical and technical FPGA design analysis based on machine learning

A Guitián, R Cayssials - 2024 Argentine Conference on …, 2024 - ieeexplore.ieee.org
FPGA device manufacturers offer a wide variety of choices oriented toward different kinds of
applications. Diverse FPGA parts, grouped into several devices and families, offer a wide …

MDCLCG with Square Root Carry Select Adder Technique for Hardware Security

M Sushmitha, K Jamal, M Kiran… - 2022 International …, 2022 - ieeexplore.ieee.org
Three-operand adder performs the modular arithmetic operations like addition, multiplication
and exponentiation by utilizing various cryptography algorithms. Here, the pseudo-random …

Notice of Removal: High speed Square Root Carry Select Adder using MTCMOS D-Latch in 45nm technology

A Das, SK Mandal, JK Das - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
Notice of Removal: High speed Square Root Carry Select Adder using MTCMOS D-Latch in
45nm technology | IEEE Conference Publication | IEEE Xplore Notice of Removal: High …

Computer-Aided Developments: Electronics and Communication

AK Sinha, JP Darsy - 2019 - api.taylorfrancis.com
In the digital signal processing (DSP) adders have higher precedence. Adders are the basic
blocks of the digital signal processing chips and are of different types. The different types of …

[PDF][PDF] ICAAI5GI2024 Conference CRC Press (Taylor & Francis) Sample Paper Template

U Kumar - niet.co.in
A SQRT Carry Select Adder (CSLA) design with modified full adder architecture is proposed
in this work. The regular SQRT CSLA has less delay but it is bulky when compared with …

Implementation of High Speed and Low Power Radix-4 8* 8 Booth Multiplier in CMOS 32nm Technology

RN Patel - 2017 - corescholar.libraries.wright.edu
According to Moore's law, number of transistors integrated on a single chip double every 18
months with a lot new functionality embedded, which results the increasing of delay and …

[PDF][PDF] Scheming of Resourceful Carry Select Adder for Supporting VLSI System

V GURAVAIAH - core.ac.uk
Designing of area as well as power proficient high speed systems of data logic are one of
the major considerable areas of exploration in VLSI system design. Carry Select Adder is a …