ECG encryption and identification based security solution on the Zynq SoC for connected health systems
Connected health is a technology that associates medical devices, security devices and
communication technologies. It enables patients to be monitored and treated remotely from …
communication technologies. It enables patients to be monitored and treated remotely from …
[PDF][PDF] Efficient hardware realization of advanced encryption standard algorithm using Virtex-5 FPGA
MH Rais, SM Qasim - International journal of computer science and …, 2009 - academia.edu
This paper presents an efficient hardware realization of Rijndael Advanced Encryption
Standard (AES) cryptographic algorithm using state-of-the-art Field Programmable Gate …
Standard (AES) cryptographic algorithm using state-of-the-art Field Programmable Gate …
System level hardware trojan detection using side-channel power analysis and machine learning
R Gayatri, Y Gayatri, CP Mitra, S Mekala… - 2020 5th …, 2020 - ieeexplore.ieee.org
Cyber physical systems (CPS) is a dominant technology in today's world due to its vast
variety of applications. But in recent times, the alarmingly increasing breach of privacy and …
variety of applications. But in recent times, the alarmingly increasing breach of privacy and …
[PDF][PDF] AES encryption algorithm hardware implementation: throughput and area comparison of 128, 192 and 256-bits key
S El Adib, N Raissouni - International Journal of Reconfigurable and …, 2012 - academia.edu
Advanced Encryption Standard (AES) adopted by the National Institute of Standards and
Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely …
Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely …
Aes ip for hybrid cryptosystem rsa-aes
A Nadjia, A Mohamed - … on Systems, Signals & Devices (SSD15 …, 2015 - ieeexplore.ieee.org
AES (Advanced Encryption Standard) is a symmetric-key algorithm, meaning the same key
is used for both encrypting and decrypting data. In this paper, we present three hardware …
is used for both encrypting and decrypting data. In this paper, we present three hardware …
Defense in depth approach on AES cryptographic decryption core to enhance reliability
G Yendamury, N Mohankumar - 2021 IEEE International IOT …, 2021 - ieeexplore.ieee.org
Security is need of the hour in today's world since the cyber physical systems are prone to
malicious attacks. Advanced Encryption Standard is a cryptographic algorithm which is …
malicious attacks. Advanced Encryption Standard is a cryptographic algorithm which is …
[PDF][PDF] A novel FPGA implementation of AES-128 using reduced residue of prime numbers based S-Box
MH Rais, SM Qasim - International Journal of Computer Science and …, 2009 - academia.edu
In this paper, we present a novel Field Programmable Gate Array (FPGA) implementation of
advanced encryption standard (AES-128) algorithm based on the design of high …
advanced encryption standard (AES-128) algorithm based on the design of high …
Design and Simulation of AES S-Box Towards Data Security in Video Surveillance Using IP Core Generator
M Hammad, W Elmedany… - … Conference on Innovation …, 2021 - ieeexplore.ieee.org
Broadcasting applications such as video surveillance systems are using High Definition
(HD) videos. The use of high-resolution videos increases significantly the data volume of …
(HD) videos. The use of high-resolution videos increases significantly the data volume of …
Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA
A Aziz, N Ikram - Information Processing Letters, 2010 - Elsevier
This work presents a resource efficient implementation of T-Box module of Advanced
Encryption Standard (AES) on Xilinx's Virtex-5 Field Programmable Gate Array (FPGA). The …
Encryption Standard (AES) on Xilinx's Virtex-5 Field Programmable Gate Array (FPGA). The …
FPGA implementation of Rijndael algorithm using reduced residue of prime numbers
MH Rais, SM Qasim - 2009 4th International Design and Test …, 2009 - ieeexplore.ieee.org
This paper describes the field programmable gate array (FPGA) implementation of Rijndael
algorithm based on a novel design of S-box built using reduced residue of prime numbers …
algorithm based on a novel design of S-box built using reduced residue of prime numbers …