Parade: A cycle-accurate full-system simulation platform for accelerator-rich architectural design and exploration

J Cong, Z Fang, M Gill… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
The power wall and utilization wall in today's processors have led to a focus on accelerator-
rich architecture, which will include a sea of accelerators that can achieve orders-of …

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

J Zarrin, RL Aguiar, JP Barraca - Simulation Modelling Practice and Theory, 2017 - Elsevier
The architecture design of peta-scale computing systems is complex and presents lots of
difficulties to designs, as current tools lack support for relevant features of future scenarios …

Varcatcher: A framework for tackling performance variability of parallel workloads on multi-core

W Zhang, X Ji, B Song, S Yu, H Chen… - … on Parallel and …, 2016 - ieeexplore.ieee.org
The non-deterministic nature of multi-threaded workloads running on multi-core platforms
often leads to notable performance variability from run to run. Such variability makes …

Simulation environment based on systemc and veos for multi-core processors with virtual autosar ecus

M Urbina, Z Owda… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
The extension of time-triggered message-based on-chip architectures towards an
AUTOSAR MPSoC platform helps to achieve the AUTOSAR goals, in particular with respect …

Co-simulation framework for networked multi-core chips with interleaving discrete event simulation tools

Z Owda, M Abuteir… - 2015 IEEE 20th …, 2015 - ieeexplore.ieee.org
The simulation of networked multi-core chips is a significant research problem in large
embedded applications. Although multi-core processors in embedded systems offer …

Prophet: A parallel instruction-oriented many-core simulator

W Zhang, X Ji, Y Lu, H Wang, H Chen… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Most existing computer architecture simulators are cycle oriented, ie, they are driven cycle
by cycle. However, frequent switches among simulation contexts, excessive buffer accesses …

A very fast trace-driven simulation platform for chip-multiprocessors architectural explorations

MES Elrabaa, A Hroub, MF Mudawar… - … on Parallel and …, 2017 - ieeexplore.ieee.org
Simulation is the main tool for computer architects and parallel application developers for
developing new architectures and parallel algorithms on many-core machines. Simulating a …

Co-simulation framework for autosar multi-core processors with message-based network-on-chips

M Urbina, H Ahmadian… - 2016 IEEE 14th …, 2016 - ieeexplore.ieee.org
Simulation environments play a very important role in the development of embedded
systems helping system architects in exploring design decisions. However, the simulation of …

The Xpress transfer protocol

AD Whaley - [1989] Proceedings. 14th Conference on Local …, 1989 - computer.org
Abstract Graphic Processing Units (GPUs) have emerged as a new general purpose
computing platform that attracts significant research efforts. Currently, GPU architecture …

Epsim: A scalable and parallel Marssx86 simulator with exploiting epoch-based execution

M Kim, C Park, M Han, Y Han, SW Kim - IEEE Access, 2018 - ieeexplore.ieee.org
In general, a detailed modeling and evaluation of computer architectures make a cycle-
accurate simulator necessary. As the architectures become increasingly complex for …