Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

F Minnella, J Cortadella, MR Casu, MT Lazarescu… - IEEE …, 2023 - ieeexplore.ieee.org
Flip-flops are the most used sequential elements in synchronous circuits, but designs based
on latches can operate at higher frequencies and occupy less area. Techniques to increase …

Hold-time violation analysis and fixing in near-threshold region

MS Golanbari, S Kiamehr… - 2016 26th International …, 2016 - ieeexplore.ieee.org
Operating in the Near Threshold Voltage (NTV) region improves the energy-efficiency of
CMOS circuits by an order of magnitude. However, the number of hold-time violations …

Exploring circuit robustness to power supply variation in low-voltage latch and register-based digital systems

A Roy, BH Calhoun - 2016 IEEE International Symposium on …, 2016 - ieeexplore.ieee.org
This paper compares the impact of power supply variation on the performance of register-
based and latch-based digital circuits. A 32-tap, 16-bit FIR filter is fabricated using both flip …

Optimized design of an LSSD scan cell

LR Juracy, MT Moreira, FA Kuentzer… - … Transactions on Very …, 2016 - ieeexplore.ieee.org
Type D flip-flop cell and its scannable version called Muxed-D are the most used sequential
components in cell-based synchronous designs because it simplifies timing analysis and it …

A comprehensive stochastic design methodology for hold-timing resiliency in voltage-scalable design

Z Chen, H Wang, G Xie, J Gu - IEEE Transactions on Very …, 2018 - ieeexplore.ieee.org
In order to fulfill different demands between ultralow energy consumption and high
performance, integrated circuits are being designed to operate across a large range of …

Low power latch based design with smart retiming

K Singh, H Jiao, J Huisken, H Fatemi… - … on Quality Electronic …, 2018 - ieeexplore.ieee.org
Flip-flops and latches are two options to construct pipelines in digital integrated circuits (ICs).
In this paper, the implications for converting a flip-flop based design to a latch-based design …

Asynchronous Stochastic Computing

P Gonzalez-Guerrero, MR Stan - 2019 53rd Asilomar …, 2019 - ieeexplore.ieee.org
Asynchronous Stochastic Computing (ASC) leverages Synchronous Stochastic Computing
(SSC) advantages and addresses its drawbacks. In SSC a multiplier is a single AND gate …

[PDF][PDF] Mix & Latch: High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops

F Minnella - 2024 - tesidottorato.depositolegale.it
Sequential circuits often use flip-flops (FFs) or latches for data storage. Latches have
advantages in error-resilient applications, lower supply voltage operation, reduced power …

[PDF][PDF] Voltage stacking for near/sub-threshold operation

K Singh - 2021 - research.tue.nl
In recent years, an explosive growth of small, battery-powered devices for low power
embedded applications, such as Internet-of-Things, wearable sensors, and biomedical …

[PDF][PDF] Modeling and Design for Low Power and Variation Tolerance in Integrated Circuits

D Kamakshi - 2017 - scholar.archive.org
Modern integrated circuits ranging from ultra-low power internet-of-things devices to high-
performance processors cater to a wide spectrum of applications and notably aid in …