FinFETs: From devices to architectures
D Bhattacharya, NK Jha - Advances in Electronics, 2014 - Wiley Online Library
Since Moore's law driven scaling of planar MOSFETs faces formidable challenges in the
nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to …
nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to …
Progress in nanoscale dry processes for fabrication of high-aspect-ratio features: How can we control critical dimension uniformity at the bottom?
K Ishikawa, K Karahashi, T Ishijima… - Japanese Journal of …, 2018 - iopscience.iop.org
In this review, we discuss the progress of emerging dry processes for nanoscale fabrication
of high-aspect-ratio features, including emerging design technology for manufacturability …
of high-aspect-ratio features, including emerging design technology for manufacturability …
FinFET circuit design
P Mishra, A Muttreja, NK Jha - Nanoelectronic circuit design, 2011 - Springer
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the
nanoscale. FinFETs are double-gate devices. The two gates of a FinFET can either be …
nanoscale. FinFETs are double-gate devices. The two gates of a FinFET can either be …
Handling conditional discrimination
Historical data used for supervised learning may contain discrimination. We study how to
train classifiers on such data, so that they are discrimination free with respect to a given …
train classifiers on such data, so that they are discrimination free with respect to a given …
Recent trend of FinFET devices and its challenges: A review
Recent technological demand of FinFETs have been explored and reviewed in this work.
The downscaling of the conventional MOSFET urge to the researchers to innovate new …
The downscaling of the conventional MOSFET urge to the researchers to innovate new …
Geometry dependence of total-dose effects in bulk FinFETs
<? Pub Dtl=""?> The total ionizing dose (TID) response of bulk FinFETs is investigated for
various geometry variations, such as fin width, channel length, and fin pitch. The buildup of …
various geometry variations, such as fin width, channel length, and fin pitch. The buildup of …
FinCACTI: Architectural analysis and modeling of caches with deeply-scaled FinFET devices
This paper presents FinCACTI, a cache modeling tool based on CACTI which also supports
deeply-scaled FinFET devices as well as more robust SRAM cells. In particular, FinFET …
deeply-scaled FinFET devices as well as more robust SRAM cells. In particular, FinFET …
Design of logic gates and flip-flops in high-performance FinFET technology
AN Bhoj, NK Jha - IEEE transactions on very large scale …, 2013 - ieeexplore.ieee.org
With the emergence of nonplanar CMOS devices at the 22-nm node and beyond, it is highly
likely that multigate device adoption will occur in a high-performance process technology …
likely that multigate device adoption will occur in a high-performance process technology …
Tunnel FETs for ultra-low voltage digital VLSI circuits: Part II–Evaluation at circuit level and design perspectives
M Alioto, D Esseni - IEEE Transactions on Very Large Scale …, 2014 - ieeexplore.ieee.org
In Part II of this paper, the potential of tunnel FETs (TFETs) for ultra-low voltage (ULV)/ultra-
low power (ULP) operation at 32-nm node is investigated through Verilog-A simulations of …
low power (ULP) operation at 32-nm node is investigated through Verilog-A simulations of …
Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells
Vertical tunnel field-effect transistors (VTFETs) have been extensively explored to overcome
the scaling limits and to improve on-current (ION) compared to standard lateral device …
the scaling limits and to improve on-current (ION) compared to standard lateral device …