A time-interleaved digital-to-analog converter up to 118 GS/s with integrated analog multiplexer in 28-nm FD-SOI CMOS technology
D Widmann, T Tannert, XQ Du, T Veigel… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
To enhance sampling rates of CMOS digital-to-analog converters (DACs), analog
multiplexing of several DAC output signals in the time domain provides a solution. In this …
multiplexing of several DAC output signals in the time domain provides a solution. In this …
A 56-Gb/s reconfigurable silicon-photonics transmitter using high-swing distributed driver and 2-tap in-segment feed-forward equalizer in 65-nm CMOS
This article presents a reconfigurable silicon-photonics transmitter (TX) for short-reach
optical interconnects. The proposed hybrid-integrated TX combines a 65-nm CMOS driver …
optical interconnects. The proposed hybrid-integrated TX combines a 65-nm CMOS driver …
A rail-to-rail high speed comparator with LVDS output in 0.18-μm SiGe BiCMOS Technology
Q Sun, R Tu, J Xie, Y Gong, S Wu, J Li, Z Luo - Integration, 2024 - Elsevier
Achieving low propagation delay in comparators under low input overdrive voltage is
challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed …
challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed …
A Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links
C Zamarreno-Ramos… - … Circuits and Systems, 2012 - ieeexplore.ieee.org
This paper presents a low power switchable current mode driver/receiver I/O pair for high
speed serial transmission of asynchronous address event representation (AER) information …
speed serial transmission of asynchronous address event representation (AER) information …
A 5-gbps serializer asic in 130 nm for high-speed front-end readout applications
C Meng, T Guo, T Xiong, Q Chen, Z Guo… - Journal of …, 2022 - iopscience.iop.org
This paper presents the design and the test results of a low-power 5 Gbps 10: 1 serializer
chip with the self-check function based on a standard 130 nm CMOS technology. This …
chip with the self-check function based on a standard 130 nm CMOS technology. This …
Design of 2Gb/s LVDS transmitter and 3Gb/s LVDS receiver for optical communication in 0.18 μm CMOS technology
H Hui, L Jia, S Lingling… - 2011 China-Japan Joint …, 2011 - ieeexplore.ieee.org
Design of a high performance CMOS LVDS transceiver in optical communication application
is presented. The proposed LVDS transceiver is composed of a transmitter (TX) circuit and a …
is presented. The proposed LVDS transceiver is composed of a transmitter (TX) circuit and a …
Spacetime frequency-multiplexed Digital-RF array receivers with reduced ADC count
Wireless systems operating at mm-wave frequencies require dense antenna arrays to
achieve directional gain for overcoming high path loss. Digital mm-wave arrays retain spatial …
achieve directional gain for overcoming high path loss. Digital mm-wave arrays retain spatial …
A 1.8 áV low power 5áGbps PMOS-based LVDS output driver with good return loss performance
This paper presents a novel design topology of a 5áGbps PMOS-based low voltage
differential signaling (LVDS) voltage mode output driver. The topology is designed to meet …
differential signaling (LVDS) voltage mode output driver. The topology is designed to meet …
A novel SST transmitter with mutually decoupled impedance self-calibration and equalization
S Chen, L Yang, H Jing, F Zhang… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
A low power source-synchronous source-series-terminated (SST) transmitter (Tx) in 65 nm
CMOS technology is presented. The Tx, comprised of nine data/control channels, a …
CMOS technology is presented. The Tx, comprised of nine data/control channels, a …
A power efficient 3-Gbits/s 1.8 V PMOS-based LVDS output driver
HW Marar, K Abugharbieh… - 2012 19th IEEE …, 2012 - ieeexplore.ieee.org
This paper presents a new topology of a PMOS based LVDS voltage-mode output driver.
This topology is designed to meet the requirements of low power consumption and high data …
This topology is designed to meet the requirements of low power consumption and high data …