Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units
(ALUs) of modern computing systems. Recently, there have been massive research interests …

A review on CMOS delay lines with a focus on the most frequently used techniques for high-
resolution delay step is presented. The primary types, specifications, delay circuits, and …

Physical unclonable functions (PUFs) have emerged as a promising security primitive for
low-cost authentication and cryptographic key generation. However, PUF stability with …

In this paper, the effect of process variations on delay is analyzed in depth for both static and
dynamic CMOS logic styles. Analysis allows for gaining an insight into the delay …

A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI)
technique and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic …

Inexact Circuits or circuits in which the accuracy of the output can be traded for energy or
delay savings, have been receiving increasing attention of late due to invariable …

Energy harvesting systems support the deployment of low-power microcontrollers
untethered by constant power sources or batteries, enabling long-lived deployments in a …

This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion
Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) …

In this paper, a simple approach to reduce delay variations in domino logic gates is
proposed. Previous analysis by the same authors showed that delay variations in domino …

In this paper, issues related to the physical design and layout density of FinFET standard
cells are discussed. Analysis significantly extends previous analyses, which considered the …