A survey of architectural approaches for data compression in cache and main memory systems
As the number of cores on a chip increases and key applications become even more data-
intensive, memory systems in modern processors have to deal with increasingly large …
intensive, memory systems in modern processors have to deal with increasingly large …
Base-delta-immediate compression: Practical data compression for on-chip caches
Cache compression is a promising technique to increase on-chip cache capacity and to
decrease on-chip and off-chip bandwidth usage. Unfortunately, directly applying well-known …
decrease on-chip and off-chip bandwidth usage. Unfortunately, directly applying well-known …
Challenges and future directions for energy, latency, and lifetime improvements in NVMs
Recently, non-volatile memory (NVM) technology has revolutionized the landscape of
memory systems. With many advantages, such as non volatility and near zero standby …
memory systems. With many advantages, such as non volatility and near zero standby …
A large-scale empirical study on self-admitted technical debt
Technical debt is a metaphor introduced by Cunningham to indicate" not quite right code
which we postpone making it right". Examples of technical debt are code smells and bug …
which we postpone making it right". Examples of technical debt are code smells and bug …
Adaptive cache compression for high-performance processors
AR Alameldeen, DA Wood - ACM SIGARCH Computer Architecture …, 2004 - dl.acm.org
Modern processors use two or more levels ofcache memories to bridge the rising disparity
betweenprocessor and memory speeds. Compression canimprove cache performance by …
betweenprocessor and memory speeds. Compression canimprove cache performance by …
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
BM Rogers, A Krishna, GB Bell, K Vu, X Jiang… - Proceedings of the 36th …, 2009 - dl.acm.org
As transistor density continues to grow at an exponential rate in accordance to Moore's law,
the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-chip …
the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-chip …
Linearly compressed pages: A low-complexity, low-latency main memory compression framework
Data compression is a promising approach for meeting the increasing memory capacity
demands expected in future systems. Unfortunately, existing compression algorithms do not …
demands expected in future systems. Unfortunately, existing compression algorithms do not …
C-pack: A high-performance microprocessor cache compression algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-
chip cache memory and the high latency of off-chip memory, such as dynamic random …
chip cache memory and the high latency of off-chip memory, such as dynamic random …
A robust main-memory compression scheme
M Ekman, P Stenstrom - 32nd International Symposium on …, 2005 - ieeexplore.ieee.org
Lossless data compression techniques can potentially free up more than 50% of the memory
resources. However, previously proposed schemes suffer from high access costs. The …
resources. However, previously proposed schemes suffer from high access costs. The …
MIRA: A multi-layered on-chip interconnect router architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the
interconnect delay problem for designing CMP/multi-core/SoC systems in deep sub-micron …
interconnect delay problem for designing CMP/multi-core/SoC systems in deep sub-micron …