A low-power low-noise amplifier with high CMRR for wearable healthcare applications

K Sharma, S Singh, A Sachdeva - AEU-International Journal of Electronics …, 2024 - Elsevier
Low-noise and low-power operation are important parameters of amplifier intended for
wearable healthcare applications. However, along with these parameters the amplifier must …

Design of a soft error hardened SRAM cell with improved access time for embedded systems

VK Tomar, A Sachdeva - Microprocessors and Microsystems, 2022 - Elsevier
Recent advancements in high-performance processor operation have nurtured the
requirement of low power, reliable, and fast static random-access memory (SRAM). Scaling …

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

P Praveen, RK Singh - ACM Transactions on Design Automation of …, 2023 - dl.acm.org
Power dissipation is considered one of the important issues in low power Very-large-scale
integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub …

Low power static random-access memory cell design for mobile opportunistic networks sensor nodes

A Sachdeva - Journal of Circuits, Systems and Computers, 2023 - World Scientific
In the present scenario, the devices supporting neighbor discovery are going through the
renovation phase, and crossing the classical barrier such as the trade-off between power …

A single ended, single port configuration based 9 T SRAM cell for stability enhancement

V Singhal, B Rawat, P Mittal, B Kumar - Physica Scripta, 2023 - iopscience.iop.org
The growing demand for power efficient devices and high-density memories has pushed
researchers to develop low power SRAMs. The main objective for these researches is to …

Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units

B Jeevan, K Bikshalu, K Sivani - Microprocessors and Microsystems, 2023 - Elsevier
This paper proposes a new Two-Stage Carry Select Adder (TSCSA) using a single type of
leaf cell ie, a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed …

Design of dual port 9T SRAM cell with parallel processing and high performance computing

Y Chopra, P Mittal - Physica Scripta, 2024 - iopscience.iop.org
To meet industry requirements of higher transistor count SRAM cells this paper is proposing,
a nine-transistor configuration static random access memory (SRAM) cell which is …

Optimization of the aspect ratio to enhance the power and noise-margin of a standard 6T (S6T)-SRAM cell

S Bhavani, L Gupta, A Sachdeva… - … on Emerging Research …, 2022 - ieeexplore.ieee.org
The demand for low-power, dependable and efficient static random-access memory (SRAM)
design has risen as a result of the continuous progress in computational power reduction …

Development of SRAM-APB protocol interface and verification

V Karthikeyan, K Balamurugan… - Engineering …, 2023 - iopscience.iop.org
The purpose of this mechanism is to enhance the chip's internal connections and read/write
memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such …

Design of a Power-Efficient Static Random Access Memory Cell with Enhanced Stability for Internet of Things Applications

A Sharma, V Kahol, A Sachdeva - 2024 IEEE 13th International …, 2024 - ieeexplore.ieee.org
In today's tech-driven era, where the need for swift data processing is paramount, memory
emerges as a critical component, playing a key role in ensuring the high speed functionality …