Automotive systems are currently undergoing a radical shift in the way they are designed,
implemented and deployed. Such changes impose an increased complexity and a high …

The interference co-running tasks generate on each other's timing behavior continues to be
one of the main challenges to be addressed before Multi-Processor System-on-Chip …

As real-time embedded systems are evolving in scale and complexity, the demand for a
higher performance at a minimum energy consumption has become a necessity …

We present MINOTAuR, a timing predictable open source RISC-V core based on the Ariane
core [28]. We first modify Ariane in order to make it timing predictable following the approach …

Abstract FPGA System-on-Chips (SoCs) are heterogeneous platforms that combine general-
purpose processors with a field-programmable gate array (FPGA) fabric. The FPGA fabric is …

We introduce the strictly in-order core (SIC), a timing-predictable pipelined processor core.
SIC is provably timing compositional and free of timing anomalies. This enables precise and …

For applications in worst-case execution time analysis and in security, it is desirable to
statically classify memory accesses into those that result in cache hits, and those that result …

The resource-constrained environment and the certification requirements underlying
embedded safety-critical real-time systems impose an adapted development process for …

Modern processors raise a challenge for WCET estimation, since detailed knowledge of the
processor microarchitecture is not available. This paper proposes a novel hybrid WCET …

The correctness of safety-critical systems depends on both their logical and temporal
behavior. Control-flow integrity (CFI) is a well-established and understood technique to …