FinFET based SRAMs in Sub-10nm domain
An exponential rise in transistor count, have increased the power consumption of the
modern digital system. Moreover, at lower technology node, the performance of …
modern digital system. Moreover, at lower technology node, the performance of …
Performance stability analysis of SRAM cells based on different FinFET devices in 7nm technology
MU Mohammed, A Nizam… - 2018 IEEE SOI-3D …, 2018 - ieeexplore.ieee.org
In this paper, the performances of 6T SRAM designs implemented by different FinFET
devices are compared for different pull-up, pull down and pass gate transistor (PU: PD: PG) …
devices are compared for different pull-up, pull down and pass gate transistor (PU: PD: PG) …
Improvising the Switching Ratio through Low-k / High-k Spacer and Dielectric Gate Stack in 3D FinFET - a Simulation Perspective
A Samal, KP Pradhan, SK Mohapatra - Silicon, 2021 - Springer
This paper extensively studies the spacer technology, including low-k/high-k, single/dual
dielectrics on the device performances focusing on the leakage current. The tactical use of a …
dielectrics on the device performances focusing on the leakage current. The tactical use of a …
Modeling and analysis of sub-surface leakage current in nano-MOSFET under cutoff regime
Y Swami, S Rai - Superlattices and Microstructures, 2017 - Elsevier
The high leakage current in nano-meter regimes is becoming a significant portion of power
dissipation in nano-MOSFET circuits as threshold voltage, channel length, and gate oxide …
dissipation in nano-MOSFET circuits as threshold voltage, channel length, and gate oxide …
Effect of high-K gate dielectric in-conjunction with channel parameters on the performance of FinFET based 6T SRAM
In this work, high-K gate-stack based FinFET is studied to investigate the effect of high-K
gate dielectric in-conjunction with channel thickness (T Si) and channel length (L g) on the …
gate dielectric in-conjunction with channel thickness (T Si) and channel length (L g) on the …
Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs
G Saini, S Choudhary - Microelectronics journal, 2016 - Elsevier
In this brief, we explore the electrostatics of junctionless accumulation mode (JAM) device
with asymmetric spacers to improve the device performance parameters at 20 nm …
with asymmetric spacers to improve the device performance parameters at 20 nm …
Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET
At the sub-22 nm technology node, junctionless FinFETs are regarded as advantageous
alternatives for conventional FinFET due to their simpler fabrication and uniform doping …
alternatives for conventional FinFET due to their simpler fabrication and uniform doping …
A study of emerging semi-conductor devices for memory applications
In this paper, a study of the existing SRAM (Static Random Access Memory) cell topologies
using various FET (Field Effect Transistor) low power devices has been done. Various low …
using various FET (Field Effect Transistor) low power devices has been done. Various low …
Performance and reliability of asymmetrical underlapped FinFET based 6T and 8T SRAMs in sub-10nm domain
MU Mohammed, A Nizam… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
Performance and Reliability of Asymmetrical Underlapped FinFET based 6T and 8T SRAMs in
Sub-10nm Domain Page 1 978-1-5386-7755-1/18/$31.00 ©2018 IEEE Performance and …
Sub-10nm Domain Page 1 978-1-5386-7755-1/18/$31.00 ©2018 IEEE Performance and …
Underlapped FinFET on insulator: Quasi3D analytical model
The work presented in this paper analyse the influence of gate underlap region (present
either near the source end or near the drain end) on the performance of FinFET using an …
either near the source end or near the drain end) on the performance of FinFET using an …