US PATENT DOCUMENTS 6,272.520 B1 8/2001 Sharangpani et al. 6,338,123 B2* 1/2002
Joseph et al.................. 711/144 6,704,845 B2* 3/2004 Anderson et al.............. 711.146 …

Memory bandwidth has become a major performance bottleneck as more and more cores
are integrated onto a single die, demanding more and more data from the system memory …

This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's
aggregate on-chip cache resources. Cooperative caching combines the strengths of private …

For parallelism to become tractable for mass programmers, shared-memory languages and
environments must evolve to enforce disciplined practices that ban" wild shared-memory …

Many future heterogeneous systems will integrate CPUs and GPUs physically on a single
chip and logically connect them via shared memory to avoid explicit data copying. Making …

In the many-core era, scalable coherence and on-chip interconnects are crucial for shared
memory processors. While snoopy coherence is common in small multicore systems …

To meet the demand for more powerful high-performance shared-memory servers,
multiprocessor systems must incorporate efficient and scalable cache coherence protocols …

As manycore architectures enable a large number of cores on the die, a key challenge that
emerges is the availability of memory bandwidth with conventional DRAM solutions. To …

A key challenge in architecting a CMP with many cores is maintaining cache coherence in
an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop …

It has been observed that some applications manipulate large amounts of null data.
Moreover these zero data often exhibit high spatial locality. On some applications more than …