Advanced gate-level glitch modeling using ANNs

A Vagenas, D Garyfallou, N Evmorfopoulos… - Proceedings of the 61st …, 2024 - dl.acm.org
Multiple Input Switching (MIS) effects commonly induce undesired glitch pulses at the output
of CMOS gates, potentially leading to circuit malfunction and significant power consumption …

Static Timing Analysis for Critical Path Identification in Ternary Logic Circuits.

S Abolmaali - Iranian Journal of Electrical & Electronic …, 2022 - search.ebscohost.com
In this article, a critical path identification method is proposed for ternary logic circuits. The
considered structure for the ternary circuits is based on 2: 1 multiplexers. Sensitization …