A 32 nm single-ended single-port 7T static random access memory for low power utilization
In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single
bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV …
bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV …
Design and Performance Analysis of Modern Computational Storage Devices: A Systematic Review
SA Shirke - Expert Systems with Applications, 2024 - Elsevier
Abstract Computational Storage Devices (CSDs), also known as In-Storage Compute or In-
Suit Processing, offer higher computing power than traditional storage devices (SD). The …
Suit Processing, offer higher computing power than traditional storage devices (SD). The …
A FinFET-based low-power, stable 8T SRAM cell with high yield
E Mani, P Nimmagadda, SJ Basha… - … -International Journal of …, 2024 - Elsevier
Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data
and respond quickly to requests. However, achieving low-power and stable SRAM cells …
and respond quickly to requests. However, achieving low-power and stable SRAM cells …
A reliable and temperature variation tolerant 7T SRAM cell with single bitline configuration for low voltage application
Static random access memory is a key component for most microprocessor-based digital
devices. With the declining technology node and reducing supply voltage, it is essential to …
devices. With the declining technology node and reducing supply voltage, it is essential to …
A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications
E Abbasian, M Gholipour - International Journal of Circuit …, 2022 - Wiley Online Library
The design of power‐efficient SRAM cells is necessary for biomedical applications such as
body area networks (BANs) to extent their battery life. SRAM cell's power consists of two …
body area networks (BANs) to extent their battery life. SRAM cell's power consists of two …
Design and investigation of stability‐and power‐improved 11T SRAM cell for low‐power devices
E Abbasian, S Birla… - International Journal of …, 2022 - Wiley Online Library
The modern system‐on‐chips require stable and low‐power SRAM cells due to technology
scaling and limited sources of energy. Therefore, a stability‐and power‐improved 11T …
scaling and limited sources of energy. Therefore, a stability‐and power‐improved 11T …
Improved read/write assist mechanism for 10‐transistor static random access memory cell
E Abbasian, M Gholipour - International Journal of Circuit …, 2022 - Wiley Online Library
This paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write
assist mechanism, improving both read static noise margin (RSNM) and write static noise …
assist mechanism, improving both read static noise margin (RSNM) and write static noise …
One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications
This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell
appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells …
appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells …
Modified decoupled sense amplifier with improved sensing speed for low-voltage differential SRAM
A modified decoupled sense amplifier (MDSA) and modified decoupled sense amplifier with
NMOS foot-switch is proposed for improved sensing in differential SRAM for low-voltage …
NMOS foot-switch is proposed for improved sensing in differential SRAM for low-voltage …
Helimagnet-based nonvolatile multi-bit memory units
In this Letter, we present a design of a helimagnet-based emerging memory device that is
capable of storing multiple bits of information per device. The device consists of a …
capable of storing multiple bits of information per device. The device consists of a …