Single-clocked digital systems are largely a thing of the past. Although most digital circuits
remain synchronous, many designs feature multiple clock domains, often running at different …

VLSI systems are often constructed from a multitude of independently clocked synchronous
IP blocks. Unfortunately, while a synchronous design style may produce efficient block level …

Various kinds of asynchronous interconnect and synchronisation mechanisms are being
proposed for designing low power, low emission and high-speed SOCs. They facilitate …

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone
to synchronization failures if the delay of their locally-generated clock tree is not considered …

Pausible clocking based globally-asynchronous locally-synchronous (GALS) system design
has been proven a promising approach to SoCs and NoCs. In this paper, we analyze the …

Power management is an important requirement for battery powered or battery operated
microprocessor based systems Such as laptop computers, notebook computers, palmtop …

We investigate the problem of designing interface circuits for rationally clocked modules in
GALS systems. As a key contribution, we show that knowledge of flow-control protocols can …

Synchronizers typically incur long latency of multiple-clock cycles, resulting in low
throughput. This paper presents two novel fast synchronizers, both based on two-phase …

Abstract First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of
data between processing blocks. High performance and high complexity digital systems …

This paper presents an architecture and a wrapper synthesis approach for the design of
multi-clock systems-on-chips. We build upon the initial work on multi-clock latency …