Full-swing gate diffusion input logic—case-study of low-power CLA adder design
A Morgenshtein, V Yuzhaninov, A Kovshilovsky, A Fish - Integration, 2014 - Elsevier
Abstract Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The proposed
methodology is applied to a 40 nm Carry Look Ahead Adder (CLA). The CLA is implemented …
methodology is applied to a 40 nm Carry Look Ahead Adder (CLA). The CLA is implemented …
Flexible circuits and architectures for ultralow power
BH Calhoun, JF Ryan, S Khanna… - Proceedings of the …, 2010 - ieeexplore.ieee.org
Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-
power (ULP) applications with low performance requirements. However, a large range of …
power (ULP) applications with low performance requirements. However, a large range of …
Subthreshold dual mode logic
A Kaizerman, S Fisher, A Fish - IEEE Transactions on Very …, 2012 - ieeexplore.ieee.org
In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to
operate in the subthreshold region. The proposed logic family can be switched between …
operate in the subthreshold region. The proposed logic family can be switched between …
An ultra-low-energy multi-standard JPEG co-processor in 65 nm CMOS with sub/near threshold supply voltage
We present a design technique for (near) subthreshold operation that achieves ultra low
energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic …
energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic …
[HTML][HTML] Energy efficient design for body sensor nodes
This paper describes the hardware requirements and design constraints that derive from
unique features of body sensor networks (BSNs). Based on the BSN requirements, we …
unique features of body sensor networks (BSNs). Based on the BSN requirements, we …
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly
restricts low voltage operation since it results in a low ON to OFF current ratio at low supply …
restricts low voltage operation since it results in a low ON to OFF current ratio at low supply …
Low-power circuit analysis and design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly
restricts low-voltage operation since it results in a low ON-to-OFF current ratio at low supply …
restricts low-voltage operation since it results in a low ON-to-OFF current ratio at low supply …
[图书][B] Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits
N Reynders, W Dehaene - 2015 - Springer
These days the Internet of Things (IoT) is the big focus when conceiving digital systems.
Given the billions of nodes that are ultimately projected for IoT, low energy signal processing …
Given the billions of nodes that are ultimately projected for IoT, low energy signal processing …
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits
under timing constraints, considering the practical case of an 8-bit multiplier. We first show …
under timing constraints, considering the practical case of an 8-bit multiplier. We first show …
A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS
JF Ryan, BH Calhoun - IEEE Custom Integrated Circuits …, 2010 - ieeexplore.ieee.org
This paper presents a sub-threshold Field Programmable Gate Array (FPGA) that uses a low-
swing dual-V DD global interconnect fabric to reduce energy and improve delay. A 90nm …
swing dual-V DD global interconnect fabric to reduce energy and improve delay. A 90nm …