Dsagen: Synthesizing programmable spatial accelerators
Domain-specific hardware accelerators can provide orders of magnitude speedup and
energy efficiency over general purpose processors. However, they require extensive manual …
energy efficiency over general purpose processors. However, they require extensive manual …
FlexGrip: A soft GPGPU for FPGAs
K Andryc, M Merchant, R Tessier - … International Conference on …, 2013 - ieeexplore.ieee.org
Over the past decade, soft microprocessors and vector processors have been extensively
used in FPGAs for a wide variety of applications. However, it is difficult to straightforwardly …
used in FPGAs for a wide variety of applications. However, it is difficult to straightforwardly …
HMFlow: Accelerating FPGA compilation with hard macros for rapid prototyping
C Lavin, M Padilla, J Lamprecht… - 2011 IEEE 19th …, 2011 - ieeexplore.ieee.org
The FPGA compilation process (synthesis, map, place, and route) is a time consuming task
that severely limits designer productivity. Compilation time can be reduced by saving …
that severely limits designer productivity. Compilation time can be reduced by saving …
DART: A programmable architecture for NoC simulation on FPGAs
D Wang, NE Jerger, JG Steffan - Proceedings of the Fifth ACM/IEEE …, 2011 - dl.acm.org
The increased demand for on-chip communication bandwidth as a result of the multi-core
trend has made networks on-chip (NoCs) a compelling choice for the communication …
trend has made networks on-chip (NoCs) a compelling choice for the communication …
Rapid prototyping tools for FPGA designs: RapidSmith
C Lavin, M Padilla, P Lundrigan… - … Conference on Field …, 2010 - ieeexplore.ieee.org
Designer productivity for FPGA design is significantly limited by the time-consuming nature
of the FPGA compilation process (synthesis, map, placement, and routing). However …
of the FPGA compilation process (synthesis, map, placement, and routing). However …
DuCNoC: A high-throughput FPGA-based NoC simulator using dual-clock lightweight router micro-architecture
On-chip interconnections play an important role in multi/many-processor systems-on-chip
(MPSoCs). In order to achieve efficient optimization, each specific application must utilize a …
(MPSoCs). In order to achieve efficient optimization, each specific application must utilize a …
AdapNoC: A fast and flexible FPGA-based NoC simulator
Network on Chip (NoC) is the most common interconnection platform for multiprocessor
systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a …
systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a …
Fast and cycle-accurate emulation of large-scale networks-on-chip using a single fpga
Modeling and simulation/emulation play a major role in research and development of novel
Networks-on-Chip (NoCs). However, conventional software simulators are so slow that …
Networks-on-Chip (NoCs). However, conventional software simulators are so slow that …
AcENoCs: A configurable HW/SW platform for FPGA accelerated NoC emulation
S Lotlikar, V Pai, PV Gratz - 2011 24th Internatioal Conference …, 2011 - ieeexplore.ieee.org
The heterogeneous nature of the modern day applications has resulted in widespread use
of Multicore SoC architectures. The emerging Network-On-Chip (NoC) interconnect …
of Multicore SoC architectures. The emerging Network-On-Chip (NoC) interconnect …
Emulation and verification framework for MPSoC based on NoC and RISC-V
M Khamis, S El-Ashry, M AbdElsalam… - Design Automation for …, 2022 - Springer
Nowadays, embedded systems have multiprocessing capabilities to meet the complexity of
modern applications, such as signal processing and multimedia. However, as the …
modern applications, such as signal processing and multimedia. However, as the …