PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms
DRAM consists of multiple resources called banks that can be accessed in parallel and
independently maintain state information. In Commercial Off-The-Shelf (COTS) multicore …
independently maintain state information. In Commercial Off-The-Shelf (COTS) multicore …
Bounding memory interference delay in COTS-based multi-core systems
In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be
delayed by other tasks running simultaneously on other cores due to interference in the …
delayed by other tasks running simultaneously on other cores due to interference in the …
T-CREST: Time-predictable multi-core architecture for embedded systems
M Schoeberl, S Abbaspour, B Akesson… - Journal of Systems …, 2015 - Elsevier
Real-time systems need time-predictable platforms to allow static analysis of the worst-case
execution time (WCET). Standard multi-core processors are optimized for the average case …
execution time (WCET). Standard multi-core processors are optimized for the average case …
Parallelism-aware memory interference delay analysis for COTS multicore systems
In modern Commercial Off-The-Shelf (COTS) mul-ticore systems, each core can generate
many parallel memory requests at a time. The processing of these parallel requests in the …
many parallel memory requests at a time. The processing of these parallel requests in the …
Bounding and reducing memory interference in COTS-based multi-core systems
In multi-core systems, main memory is a major shared resource among processor cores. A
task running on one core can be delayed by other tasks running simultaneously on other …
task running on one core can be delayed by other tasks running simultaneously on other …
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems
Mixed-time critical systems are real-time systems that accommodate both hard real-time
(HRT) and soft realtime (SRT) tasks. HRT tasks mandate a gurantee on the worstcase …
(HRT) and soft realtime (SRT) tasks. HRT tasks mandate a gurantee on the worstcase …
Designing predictable cache coherence protocols for multi-core real-time systems
This article addresses the challenge of allowing simultaneous and predictable accesses to
shared data on multi-core systems. We propose a collection of predictable cache coherence …
shared data on multi-core systems. We propose a collection of predictable cache coherence …
Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources
The embedded system industry is facing an increasing pressure for migrating from single-
core to multi-and many-core platforms for size, performance and cost purposes. Real-time …
core to multi-and many-core platforms for size, performance and cost purposes. Real-time …
A dual-criticality memory controller (DCmc): Proposal and evaluation of a space case study
J Jalle, E Quinones, J Abella, L Fossati… - 2014 IEEE Real …, 2014 - ieeexplore.ieee.org
Multicore Dual-Criticality systems comprise two types of applications, each with a different
criticality level. In the space domain these types are referred as payload and control …
criticality level. In the space domain these types are referred as payload and control …
A mixed critical memory controller using bank privatization and fixed priority scheduling
L Ecco, S Tobuschat, S Saidi… - 2014 IEEE 20th …, 2014 - ieeexplore.ieee.org
Mixed critical platforms are those in which applications that have different criticalities, ie
different levels of importance for system safety, coexist and share resources. Such platforms …
different levels of importance for system safety, coexist and share resources. Such platforms …