The year 2011 marked an important transition for FPGA high-level synthesis (HLS), as it
went from prototyping to deployment. A decade later, in this article, we assess the progress …

We review the problem of automating hardware-aware architectural design process of Deep
Neural Networks (DNNs). The field of Convolutional Neural Network (CNN) algorithm design …

We propose a novel hardware and software co-exploration framework for efficient neural
architecture search (NAS). Different from existing hardware-aware NAS which assumes a …

DNN accelerators provide efficiency by leveraging reuse of activations/weights/outputs
during the DNN computations to reduce data movement from DRAM to the chip. The reuse is …

Binary neural networks (BNNs) have 1-bit weights and activations. Such networks are well
suited for FPGAs, as their dominant computations are bitwise arithmetic and the memory …

Analyzing videos and images captured by unmanned aerial vehicles or aerial drones is an
emerging application attracting significant attention from researchers in various areas of …

Neural Architecture Search (NAS) methods have been growing in popularity. These
techniques have been fundamental to automate and speed up the time consuming and error …

Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating
platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units …

Developing object detection and tracking on resource-constrained embedded systems is
challenging. While object detection is one of the most compute-intensive tasks from the …

Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for
domain-specific hardware accelerators (ie, DNN chips). However, designing DNN chips is …