An ultra-low-power fully-static contention-free flip-flop with complete redundant clock transition and transistor elimination
A redundancy eliminated flip-flop (REFF) is proposed targeting wide-range voltage
scalability (1–0.3 V). Two types of redundancies are eliminated in the REFF to achieve low …
scalability (1–0.3 V). Two types of redundancies are eliminated in the REFF to achieve low …
Design of a dual change-sensing 24t flip-flop in 65 nm cmos technology for ultra low-power system chips
In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual
change-sensing scheme is discussed. Further, in order to reduce power consumption, a new …
change-sensing scheme is discussed. Further, in order to reduce power consumption, a new …
[HTML][HTML] Design of low delay low power hybrid logic based flip-flop using FinFET
SS Vali - e-Prime-Advances in Electrical Engineering …, 2024 - Elsevier
The need for a low-power and high-speed technology for computation of digital signals is
rising due to the fast growth of technological innovations. Flip-flops serve as fundamental …
rising due to the fast growth of technological innovations. Flip-flops serve as fundamental …
22nm CMOS pW Standby Power Flip-Flops with/without Security using Dynamic Leakage Suppression Logic
Two circuit designs of pW standby power flip-flop (FF) in 22nm ULL process, targeting low-
voltage (down to 0.2 V), and low-frequency IoT applications are presented. The proposed …
voltage (down to 0.2 V), and low-frequency IoT applications are presented. The proposed …
NTV 영역에서안정적으로동작가능한저전력16-트랜지스터단상클럭Flip-Flop
석준하， 김혜선， 김소영 - 전자공학회논문지, 2024 - dbpia.co.kr
본 논문은 Near-threshold voltage (NTV) 영역에서 안정적으로 동작 가능한 새로운 저전력 16-
transistor single-phase clock (16TSPC) flip-flop (FF) 구조를 제안한다. 16TSPC 는 contention …
transistor single-phase clock (16TSPC) flip-flop (FF) 구조를 제안한다. 16TSPC 는 contention …
Low Power Flip-Flop Circuit with a Minimization of Internal Node Transition
H Choi, S Yun, S Kim, M Song - Transactions on Semiconductor …, 2023 - koreascience.kr
This paper presents a low-power flip-flop (FF) circuit that minimizes the transition of internal
nodes by using a dual change-sensing method. The proposed dual change-sensing FF …
nodes by using a dual change-sensing method. The proposed dual change-sensing FF …