A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …

A highly integrated ultra-low-cost high-performance Bluetooth 3.0+ EDR SoC is
implemented in 0.11-μm digital CMOS technology. The transceiver has an integrated balun …

This work elucidates how the combined effects of power-amplifier distortion and local-
oscillator (LO) pulling adversely impact a wireless direct-conversion transmitter (DCT) that …

This paper studies the local oscillator (LO) pulling problems associated with a direct-
conversion transmitter (DCT) that uses non-constant envelope modulation schemes. The …

This brief presents the injection pulling mitigation of a voltage-controlled oscillator (VCO)
using a novel honeycomb-shaped planar inductor. Due to the twisted routes of the sub-coils …

This article presents the pulling mitigation scheme implemented in the frequency synthesizer
integrated with the dual-band narrowband-internet-of-things (NB-IoT) transmitter (TX). The …

In this work, a low cost Bluetooth Low Energy (BLE) transceiver for wireless sensor network
(WSN) applications, with a receiver (RX) matching network reusing power amplifier (PA) …

Phase-locked loops (PLLs) are widely deployed in most electronic systems to generate a
desired clock frequency, perform clock data recovery (CDR), and achieve frequency or …

A new formulation is presented for the analysis of phase-locked loops (PLL). It is based on
the use of a realistic reduced-order model for the voltage-controlled oscillator, extracted from …

As technology is scaling down by reducing the lateral and vertical dimensions of transistors.
It becomes necessary to reduce the supply voltage, enhancing lower power dissipation and …