Evaluating Reduced-Tag MRAM Architectures for Enhanced Performance in Last-Level Caches

I Singh, B Raj, M Khosla - 2024 First International Conference …, 2024 - ieeexplore.ieee.org
This paper evaluates the performance benefits of Spin-Orbit Torque Magnetic RAM (SOT-
MRAM) and Spin Transfer Torque Magnetic RAM (STT-MRAM) in Last-Level Caches (LLCs) …

High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM

J Wang, Y Zhang, C Lian, G Wang… - 2019 IEEE/ACM …, 2019 - ieeexplore.ieee.org
This paper proposes a novel voltage sensing scheme in order to improve reliability and
reduce read delay for spin transfer torque magnetic random access memory (STT-MRAM) …

Energy minimization in the STT-RAM-based high-capacity last-level caches

E Khajekarimi, K Jamshidi, A Vafaei - The Journal of Supercomputing, 2019 - Springer
Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in
the large last-level caches (L 3 Cs) on account of low leakage, the absence of refresh …

Role of cache replacement policies in high performance computing systems: a survey

P Das - … and Computing: First International Conference, CNC …, 2019 - Springer
Cache replacement policies play important roles in efficiently processing the current big data
applications. The performance of any high performance computing system is highly …

Exploiting bit-level write patterns to reduce energy consumption in hybrid cache architecture

J Choi, H Park - IEICE Electronics Express, 2021 - jstage.jst.go.jp
A hybrid cache architecture (HCA) is introduced to alleviate the drawbacks of non-volatile
memory (NVM) technologies. Although researchers have offered meaningful ways to …

[PDF][PDF] Architecting Large Caches with Reduced Energy

J He - 2018 - utd-ir.tdl.org
First, I would like to thank my advisor, Dr. Joseph Callenes-Sloan, for his encouragement
when I encountered difficulty and frustration during my research. I want to give my sincere …