Design and Verification of a 6.25 GHz LC-Tank VCO Integrated in 65 nm CMOS Technology Operating up to 1 Grad TID

D Monda, G Ciarpi, S Saponara - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This article presents the design of an LC-Tank voltage-controlled oscillator (VCO) for space
and high-energy physics (HEP) applications. The main goal of this work is to design a …

Single-event effect responses of integrated planar inductors in 65-nm CMOS

S Biereigel, S Kulis, P Leroux, P Moreira… - IEEE transactions on …, 2021 - ieeexplore.ieee.org
This article describes a previously unreported single-event radiation effect in spiral inductors
manufactured in a commercial CMOS technology when subjected to ionizing radiation …

SISSA: The lpGBT PLL and CDR Architecture, Performance and SEE Robustness

S Biereigel, P Moreira, S Kulis, R Francisco, PV Leitao… - PoS, 2020 - cds.cern.ch
We present the design, architecture and experimental results of the low jitter Clock and Data
Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit …

Source switched charge-pump PLLs for high-dose radiation environments

J Prinzie, S Biereigel, S Kulis, P Leitao… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This article presents a radiation tolerant charge-pump phase-locked loop (PLL) with low
static phase error variability suitable for high-performance clock systems in high-dose …

A low noise fault tolerant radiation hardened 2.56 Gbps clock-data recovery circuit with high speed feed forward correction in 65 nm CMOS

S Biereigel, S Kulis, P Leitao… - … on Circuits and …, 2019 - ieeexplore.ieee.org
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is
presented for high-energy physics and space applications. The CDR employs a novel soft …

Analysis and comparison of rad-hard ring and LC-tank controlled oscillators in 65 nm for SpaceFibre applications

D Monda, G Ciarpi, S Saponara - Sensors, 2020 - mdpi.com
This work presented a comparison between two Voltage Controlled Oscillators (VCOs)
designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) …

CDP1—A data concentrator prototype for the deep underground neutrino experiment

S Miryala, D Braga, DC Christian… - … on Nuclear Science, 2019 - ieeexplore.ieee.org
The design, power analysis, and tests of a first COLDATA Prototype (CDP1) design in a 65-
nm process for the long baseline neutrino facility (LBNF) and the deep underground …

Single-Event Effects Characterization of LC-VCO PLLs in a 28-nm CMOS Technology

Z Zhang, H Djahanshahi, C Gu… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Two-photon absorption laser experiments are conducted on a low-jitter tunable hybrid
analog-digital LC-tank phase-locked loop (PLL) in a 28-nm bulk CMOS technology. The …

Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit

A Karthigeyan, S Radha… - IET Circuits, Devices & …, 2022 - Wiley Online Library
Single‐event transients (SETs) due to heavy‐ion (HI) strikes adversely affect the electronic
circuits in the sub‐100 nm regime in the radiation environment. This study proposes …

Voltage-controlled oscillator utilizing inverse-mode SiGe-HBT biasing circuit for the mitigation of single-event effects

PKC Mishu, MK Cho, A Khachatrian… - … on Nuclear Science, 2022 - ieeexplore.ieee.org
The advantages and the tradeoffs associated with the use of inverse-mode (IM) silicon–
germanium (SiGe) heterojunction bipolar transistors (HBTs) biasing circuitry in radio …