Tpp: Transparent page placement for cxl-enabled tiered-memory

HA Maruf, H Wang, A Dhanotia, J Weiner… - Proceedings of the 28th …, 2023 - dl.acm.org
The increasing demand for memory in hyperscale applications has led to memory becoming
a large portion of the overall datacenter spend. The emergence of coherent interfaces like …

A modern primer on processing in memory

O Mutlu, S Ghose, J Gómez-Luna… - … computing: from devices …, 2022 - Springer
Modern computing systems are overwhelmingly designed to move data to computation. This
design choice goes directly against at least three key trends in computing that cause …

CACTI 7: New tools for interconnect exploration in innovative off-chip memories

R Balasubramonian, AB Kahng… - ACM Transactions on …, 2017 - dl.acm.org
Historically, server designers have opted for simple memory systems by picking one of a few
commoditized DDR memory products. We are already witnessing a major upheaval in the off …

TMO: Transparent memory offloading in datacenters

J Weiner, N Agarwal, D Schatzberg, L Yang… - Proceedings of the 27th …, 2022 - dl.acm.org
The unrelenting growth of the memory needs of emerging datacenter applications, along
with ever increasing cost and volatility of DRAM prices, has led to DRAM being a major …

A survey on techniques for improving Phase Change Memory (PCM) lifetime

M Mohseni, AH Novin - Journal of Systems Architecture, 2023 - Elsevier
ABSTRACT PCMs are Non-Volatile Memories (NVMs) that store data using phase-change
semiconductors, such as silicon-chalcogenide glass. In addition to increased integration …

Evaluating STT-RAM as an energy-efficient main memory alternative

E Kültürsay, M Kandemir… - … Analysis of Systems …, 2013 - ieeexplore.ieee.org
In this paper, we explore the possibility of using STT-RAM technology to completely replace
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …

Nimble page management for tiered memory systems

Z Yan, D Lustig, D Nellans… - Proceedings of the Twenty …, 2019 - dl.acm.org
Software-controlled heterogeneous memory systems have the potential to increase the
performance and cost efficiency of computing systems. However they can only deliver on …

SCMFS: A file system for storage class memory

X Wu, ALN Reddy - Proceedings of 2011 International Conference for …, 2011 - dl.acm.org
This paper considers the problem of how to implement a file system on Storage Class
Memory (SCM), that is directly connected to the memory bus, byte addressable and is also …

Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization

KK Chang, A Kashyap, H Hassan, S Ghose… - Proceedings of the …, 2016 - dl.acm.org
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …

Data reorganization in memory using 3D-stacked DRAM

B Akin, F Franchetti, JC Hoe - ACM SIGARCH Computer Architecture …, 2015 - dl.acm.org
In this paper we focus on common data reorganization operations such as shuffle,
pack/unpack, swap, transpose, and layout transformations. Although these operations …