Tpp: Transparent page placement for cxl-enabled tiered-memory
The increasing demand for memory in hyperscale applications has led to memory becoming
a large portion of the overall datacenter spend. The emergence of coherent interfaces like …
a large portion of the overall datacenter spend. The emergence of coherent interfaces like …
A modern primer on processing in memory
Modern computing systems are overwhelmingly designed to move data to computation. This
design choice goes directly against at least three key trends in computing that cause …
design choice goes directly against at least three key trends in computing that cause …
CACTI 7: New tools for interconnect exploration in innovative off-chip memories
R Balasubramonian, AB Kahng… - ACM Transactions on …, 2017 - dl.acm.org
Historically, server designers have opted for simple memory systems by picking one of a few
commoditized DDR memory products. We are already witnessing a major upheaval in the off …
commoditized DDR memory products. We are already witnessing a major upheaval in the off …
TMO: Transparent memory offloading in datacenters
The unrelenting growth of the memory needs of emerging datacenter applications, along
with ever increasing cost and volatility of DRAM prices, has led to DRAM being a major …
with ever increasing cost and volatility of DRAM prices, has led to DRAM being a major …
A survey on techniques for improving Phase Change Memory (PCM) lifetime
M Mohseni, AH Novin - Journal of Systems Architecture, 2023 - Elsevier
ABSTRACT PCMs are Non-Volatile Memories (NVMs) that store data using phase-change
semiconductors, such as silicon-chalcogenide glass. In addition to increased integration …
semiconductors, such as silicon-chalcogenide glass. In addition to increased integration …
Evaluating STT-RAM as an energy-efficient main memory alternative
E Kültürsay, M Kandemir… - … Analysis of Systems …, 2013 - ieeexplore.ieee.org
In this paper, we explore the possibility of using STT-RAM technology to completely replace
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …
Nimble page management for tiered memory systems
Software-controlled heterogeneous memory systems have the potential to increase the
performance and cost efficiency of computing systems. However they can only deliver on …
performance and cost efficiency of computing systems. However they can only deliver on …
SCMFS: A file system for storage class memory
This paper considers the problem of how to implement a file system on Storage Class
Memory (SCM), that is directly connected to the memory bus, byte addressable and is also …
Memory (SCM), that is directly connected to the memory bus, byte addressable and is also …
Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …
latency is defined by three fundamental operations that take place within the DRAM cell …
Data reorganization in memory using 3D-stacked DRAM
In this paper we focus on common data reorganization operations such as shuffle,
pack/unpack, swap, transpose, and layout transformations. Although these operations …
pack/unpack, swap, transpose, and layout transformations. Although these operations …