A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC
In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-
bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter …
bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter …
A wideband fast start-up multi-core VCO with auto-frequency control in 0.18 μm CMOS
Y Li, B Zhou, Z Wang - IEEE Access, 2021 - ieeexplore.ieee.org
A 2.8–4.6 GHz wideband multi-core VCO with a fast start-up scheme is presented in this
brief. The proposed multi-core VCO uses a successive approximation register based auto …
brief. The proposed multi-core VCO uses a successive approximation register based auto …
A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications
E Ulusoy, E Zencir - Journal of Circuits, Systems and Computers, 2023 - World Scientific
In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a
Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10 …
Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10 …
A Low Jitter and High-Speed Flash TDC with PVT Calibration and Its Testing Methodology
This paper presents a high-resolution, low jitter, and low-power 4-bit flash time-to-digital
converter (TDC). As TDC is prone to PVT variation, NLMS-based calibration is used to …
converter (TDC). As TDC is prone to PVT variation, NLMS-based calibration is used to …
VCO Optimization in CMOS Technology Applying Metaheuristics
PR Castañeda - 2023 - inaoe.repositorioinstitucional.mx
Esta tesis se centra en la optimizacion del desempeño de dos topologías de osciladores
controlados por voltaje (VCOs) en estructura de anillo, mediante el uso de metaheurísticas …
controlados por voltaje (VCOs) en estructura de anillo, mediante el uso de metaheurísticas …