A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads

S Che, JW Sheaffer, M Boyer… - IEEE International …, 2010 - ieeexplore.ieee.org
The recently released Rodinia benchmark suite enables users to evaluate heterogeneous
systems including both accelerators, such as GPUs, and multicore CPUs. As Rodinia sees …

Efficiently exploring architectural design spaces via predictive modeling

E Ïpek, SA McKee, R Caruana, BR de Supinski… - ACM SIGOPS …, 2006 - dl.acm.org
Architects use cycle-by-cycle simulation to evaluate design choices and understand
tradeoffs and interactions among design parameters. Efficiently exploring exponential-size …

Caloree: Learning control for predictable latency and low energy

N Mishra, C Imes, JD Lafferty, H Hoffmann - ACM SIGPLAN Notices, 2018 - dl.acm.org
Many modern computing systems must provide reliable latency with minimal energy. Two
central challenges arise when allocating system resources to meet these conflicting …

Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite

A Phansalkar, A Joshi, LK John - Proceedings of the 34th annual …, 2007 - dl.acm.org
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer
designers and computer architecture researchers for pre-silicon early design analysis …

Construction and use of linear regression models for processor performance analysis

PJ Joseph, K Vaswani… - The Twelfth International …, 2006 - ieeexplore.ieee.org
Processor architects have a challenging task of evaluating a large design space consisting
of several interacting parameters and optimizations. In order to assist architects in making …

A probabilistic graphical model-based approach for minimizing energy under performance constraints

N Mishra, H Zhang, JD Lafferty… - ACM SIGARCH Computer …, 2015 - dl.acm.org
In many deployments, computer systems are underutilized--meaning that applications have
performance requirements that demand less than full system capacity. Ideally, we would …

ArchExplorer: Microarchitecture exploration via bottleneck analysis

C Bai, J Huang, X Wei, Y Ma, S Li, H Zheng… - Proceedings of the 56th …, 2023 - dl.acm.org
Design space exploration (DSE) for microarchitecture parameters is an essential stage in
microprocessor design to explore the trade-offs among performance, power, and area …

Respir: A response surface-based pareto iterative refinement for application-specific design space exploration

G Palermo, C Silvano, V Zaccaria - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
Application-specific multiprocessor systems-on-chip (MPSoCs) are usually designed by
using a platform-based approach, where a wide range of customizable parameters can be …

Measuring program similarity: Experiments with SPEC CPU benchmark suites

A Phansalkar, A Joshi, L Eeckhout… - … Analysis of Systems …, 2005 - ieeexplore.ieee.org
It is essential that a subset of benchmark programs used to evaluate an architectural
enhancement, is well distributed within the target workload space rather than clustered in …

Apparatus and method for optimizing quantifiable behavior in configurable devices and systems

H Hoffmann, J Lafferty, N Mishra - US Patent 11,009,836, 2021 - Google Patents
An apparatus and method are provided to perform constrained optimization of a constrained
property of an apparatus, which is complex due to having several components, and these …