[PDF][PDF] Design and Implementation of Demodulator and Carrier Phase Compensation System for Satellite Communication
A proposed design and FPGA implementation of a demodulator and phase compensation
system is presented. The system is simple, accurate, dissipate low power. Simulations …
system is presented. The system is simple, accurate, dissipate low power. Simulations …
Hidden attractors in dynamical models of phase-locked loop circuits: limitations of simulation in MATLAB and SPICE
During recent years it has been shown that hidden oscillations, whose basin of attraction
does not overlap with small neighborhoods of equilibria, may significantly complicate …
does not overlap with small neighborhoods of equilibria, may significantly complicate …
[HTML][HTML] Nonlinear dynamical model of Costas loop and an approach to the analysis of its stability in the large
The analysis of the stability and numerical simulation of Costas loop circuits for high-
frequency signals is a challenging task. The problem lies in the fact that it is necessary to …
frequency signals is a challenging task. The problem lies in the fact that it is necessary to …
Simulation of analog Costas loop circuits
RE Best, NV Kuznetsov, GA Leonov… - International Journal of …, 2014 - Springer
The analysis of stability and numerical simulation of Costas loop circuits for the high-
frequency signals is a challenging task. The problem lies in the fact that it is necessary to …
frequency signals is a challenging task. The problem lies in the fact that it is necessary to …
A short survey on nonlinear models of the classic Costas loop: rigorous derivation and limitations of the classic analysis
RE Best, NV Kuznetsov, OA Kuznetsova… - 2015 American …, 2015 - ieeexplore.ieee.org
Rigorous nonlinear analysis of the physical model of Costas loop-a classic phase-locked
loop (PLL) based circuit for carrier recovery, is a challenging task. Thus for its analysis …
loop (PLL) based circuit for carrier recovery, is a challenging task. Thus for its analysis …
Network of phase-locking oscillators and a possible model for neural synchronization
JRC Piqueira - Communications in Nonlinear Science and Numerical …, 2011 - Elsevier
In order to model the synchronization of brain signals, a three-node fully-connected network
is presented. The nodes are considered to be voltage control oscillator neurons (VCON) …
is presented. The nodes are considered to be voltage control oscillator neurons (VCON) …
Nonlinear analysis of classical phase-locked loops in signal's phase space
Discovery of undesirable hidden oscillations, which cannot be found by the standard
simulation, in phase-locked loop (PLL) showed the importance of consideration of nonlinear …
simulation, in phase-locked loop (PLL) showed the importance of consideration of nonlinear …
Bifurcation analysis for third-order phase-locked loops
LHA Monteiro, JRC Piqueira - IEEE Signal Processing Letters, 2004 - ieeexplore.ieee.org
Second-order phase-locked loops (PLLs) are extensively used in applications related to
recovering clock signals for synchronous demodulation in telecommunication networks. In …
recovering clock signals for synchronous demodulation in telecommunication networks. In …
Using bifurcations in the determination of lock-in ranges for third-order phase-locked loops
JRC Piqueira - Communications in Nonlinear Science and Numerical …, 2009 - Elsevier
Transmission and switching in digital telecommunication networks require distribution of
precise time signals among the nodes. Commercial systems usually adopt a master-slave …
precise time signals among the nodes. Commercial systems usually adopt a master-slave …
Modeling and filtering double-frequency jitter in one-way master–slave chain networks
AM Bueno, AA Ferreira… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
One-way master-slave (OWMS) chain networks are widely used in clock distribution systems
due to their reliability and low cost. As the network nodes are phase-locked loops (PLLs) …
due to their reliability and low cost. As the network nodes are phase-locked loops (PLLs) …