Tool supporting the co-design of control systems and their real-time implementation: current status and future directions
M Torngren, D Henriksson, KE Arzen… - … IEEE Conference on …, 2006 - ieeexplore.ieee.org
Control systems design has traditionally been treated separately from the design of its
software and hardware implementation. The increasing use of embedded control in for …
software and hardware implementation. The increasing use of embedded control in for …
Torsche scheduling toolbox for matlab
This paper presents a Matlab based Scheduling toolbox TORSCHE (Time Optimization of
Resources, SCHEduling). The toolbox offers a collection of data structures that allow the …
Resources, SCHEduling). The toolbox offers a collection of data structures that allow the …
A robust basic cyclic scheduling problem
This paper addresses the Basic Cyclic Scheduling Problem where the processing times are
affected by uncertainties. We formulate the problem as a two-stage robust optimization …
affected by uncertainties. We formulate the problem as a two-stage robust optimization …
A graph-based analysis of the cyclic scheduling problem with time constraints: schedulability and periodicity of the earliest schedule
A Munier Kordon - Journal of Scheduling, 2011 - Springer
We consider in this paper a set of generic tasks constrained by a set of uniform precedence
constraints corresponding to a natural generalization of the basic cyclic scheduling problem …
constraints corresponding to a natural generalization of the basic cyclic scheduling problem …
[HTML][HTML] Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times
P Šůcha, Z Hanzálek - Mathematical and Computer Modelling, 2008 - Elsevier
This paper presents a scheduling technique used to optimize computation speed of loops
running on architectures that may include pipelined dedicated processors. The problem …
running on architectures that may include pipelined dedicated processors. The problem …
[PDF][PDF] Implementation of the least-squares lattice with order and forgetting factor estimation for FPGA
Z Pohl, M Tichy, J Kadlec - EURASIP Journal on Advances in Signal …, 2008 - Springer
A high performance RLS lattice filter with the estimation of an unknown order and forgetting
factor of identified system was developed and implemented as a PCORE coprocessor for …
factor of identified system was developed and implemented as a PCORE coprocessor for …
Converging to periodic schedules for cyclic scheduling problems with resources and deadlines
BD de Dinechin, AM Kordon - Computers & operations research, 2014 - Elsevier
Cyclic scheduling has been widely studied because of the importance of applications in
manufacturing systems and in computer science. For this class of problems, a finite set of …
manufacturing systems and in computer science. For this class of problems, a finite set of …
Scheduling with start time related deadlines
P Sucha, Z Hanzálek - … on Robotics and Automation (IEEE Cat …, 2004 - ieeexplore.ieee.org
This work presents a scheduling problem for a monoprocessor without preemption with
timing constraints given by a task-on-node graph. The precedence relations are given by an …
timing constraints given by a task-on-node graph. The precedence relations are given by an …
Efficient FPGA implementation of equalizer for finite interval constant modulus algorithm
P Sucha, Z Hanzálek, A Hermanek… - … on Industrial Embedded …, 2006 - ieeexplore.ieee.org
This paper deals with the optimization of iterative algorithms with matrix operations or nested
loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using …
loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using …
Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm
P Šůcha, Z Hanzálek, A Heřmánek, J Schier - The Journal of VLSI Signal …, 2007 - Springer
This paper deals with the optimization of iterative algorithms with matrix operations or nested
loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using …
loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using …