Placement is one of the most critical stages in the physical synthesis flow. Circuits with
increasing numbers of cells of multirow height have brought challenges to traditional placers …

Machine learning (ML) models have been used to improve the quality of different physical
design steps, such as timing analysis, clock tree synthesis, and routing. However, so far very …

Modern circuits often contain standard cells of different row heights to meet various design
requirements. Taller cells give larger drive strengths and higher speed at the cost of larger …

Excessive dynamic IR-drop degrades the circuit performance and may lead to functional
failure. Existing IR-drop fixing techniques at the placement stage do not consider the time …

The placement stage of the physical design of very large-scale integrated circuits (VLSI)
specifies the arrangement and order of standard cells and devices within an area, and the …

A circuit design with non-integer multiple cell height (NIMCH) is more flexible for optimizing
area, timing, and power simultaneously. A cell with a larger height provides higher pin …

Due to the aggressive scaling of advanced technology nodes, multiple-row-height cells have
become more and more common in VLSI design. Consequently, the placement of cells is no …

Mixed-size cell circuits dominate in advanced technology node designs, with attendant
increases in layout complexity. The introduction of multi-row-height cells requires additional …

Conventional standard cell libraries are composed of cells of diverse logic functions, all of
which commonly and strictly maintain an equal height ie, single-row-height. However, as the …

To tackle the complexity of state-of-the-art electronic systems, silicon foundries continuously
shrink the technology nodes and electronic design automation (EDA) vendors offer …