Metrics-to-methods: Decisive reverse engineering metrics for resilient logic locking
MS Rahman, K Zamiri Azar, F Farahmandi… - Proceedings of the …, 2023 - dl.acm.org
As logic locking becomes more sophisticated and new technologies emerge (eg, laser
probing for failure analysis), the statement" logic locking is dead" will become more …
probing for failure analysis), the statement" logic locking is dead" will become more …
LLE: mitigating IC piracy and reverse engineering by last level edit
S Rahman, N Varshney, F Farahmandi… - … for Testing and …, 2023 - dl.asminternational.org
Hardware obfuscation is a proactive design-for-trust technique against integrated circuit (IC)
supply chain threats, ie, intellectual property (IP) piracy and overproduction. Many studies …
supply chain threats, ie, intellectual property (IP) piracy and overproduction. Many studies …
FPGA Bitstream Modification: Attacks and Countermeasures
M Moraitis - IEEE Access, 2023 - ieeexplore.ieee.org
Advances in Field-Programmable Gate Array (FPGA) technology in recent years have
resulted in an expansion of its usage in a very wide spectrum of applications. Apart from …
resulted in an expansion of its usage in a very wide spectrum of applications. Apart from …
Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration
The semiconductor industry has adopted heterogeneous integration (HI), incorporating
modular intellectual property (IP) blocks (chiplets) into a unified system-in-package (SiP) to …
modular intellectual property (IP) blocks (chiplets) into a unified system-in-package (SiP) to …
SHI-Lock: Enabling Co-Obfuscation for Secure Heterogeneous Integration Against RE and Cloning
With the limitations of Moore's Law and Dennard scaling in integrated circuits (ICs) on the
horizon, the concept of heterogeneous integration (HI) has gained significant traction as a …
horizon, the concept of heterogeneous integration (HI) has gained significant traction as a …
Era of Sentinel Tech: Charting Hardware Security Landscapes through Post-Silicon Innovation, Threat Mitigation and Future Trajectories
MBR Srinivas, E Konguvel - IEEE Access, 2024 - ieeexplore.ieee.org
To meet the demanding requirements of VLSI design, including improved speed, reduced
power consumption, and compact architectures, various IP cores from trusted and untrusted …
power consumption, and compact architectures, various IP cores from trusted and untrusted …
From Full-Custom to Gate-Array ASIC for Hardware IP Protection
HM Kamali - 2024 IEEE 17th Dallas Circuits and Systems …, 2024 - ieeexplore.ieee.org
The employment of fully reconfigurable logic and routing modules represents a promising
and potentially resilient approach to combating intellectual property (IP) piracy and the …
and potentially resilient approach to combating intellectual property (IP) piracy and the …
Optimizing RTL Code Obfuscation: New Methods Based on XML Syntax Tree
H Yi, J Zhang, S Liu - Applied Sciences, 2023 - mdpi.com
As the most widely used description code in digital circuits and system on chip (SoC), the
security of register transfer level (RTL) code is extremely critical. Code obfuscation is a …
security of register transfer level (RTL) code is extremely critical. Code obfuscation is a …
Rethinking Hardware Watermark
M Tehranipoor, K Zamiri Azar, N Asadizanjani… - Hardware Security: A …, 2024 - Springer
Intellectual property (IP) cores are essential to creating modern system-on-chips (SoCs).
Protecting the IPs deployed in modern SoCs has become more difficult as the IP houses …
Protecting the IPs deployed in modern SoCs has become more difficult as the IP houses …
Materials for Hardware Security
M Tehranipoor, K Zamiri Azar, N Asadizanjani… - Hardware Security: A …, 2024 - Springer
Hardware security for integrated circuits (ICs) is becoming an increasingly relevant issue for
semiconductor devices, and physical inspection methods are normally used as counter …
semiconductor devices, and physical inspection methods are normally used as counter …