A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH Modulator Dissipating 16 mW Power
This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-
sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The …
sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The …
A 950 MHz clock 47.5 MHz BW 4.7 mW 67 dB SNDR discrete time delta sigma ADC leveraging ring amplification and split-source comparator based quantizer in 28 …
This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring
amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) …
amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) …
A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time resolution-enhanced sturdy MASH Delta–Sigma modulator using source-follower-based integrators
This paper presents a 2-2 discrete-time (DT) resolution-enhanced sturdy multi-stage noise-
shaping (SMASH) delta-sigma modulator. It uses source-follower-based integrators to …
shaping (SMASH) delta-sigma modulator. It uses source-follower-based integrators to …
A 81-dB Dynamic Range 16-MHz Bandwidth Modulator Using Background Calibration
SH Wu, JT Wu - IEEE journal of solid-state circuits, 2013 - ieeexplore.ieee.org
A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm
CMOS technology. It combines low-complexity circuits and digital calibrations to achieve …
CMOS technology. It combines low-complexity circuits and digital calibrations to achieve …
A 24-bit sigma-delta ADC with configurable chopping scheme
L Li, X Cheng, Z Zhang, J Zeng, X Zeng - IEICE Electronics Express, 2019 - jstage.jst.go.jp
This paper presents a low-power high-precision sigma-delta analog-to-digital converter
(ADC) mainly used for DC measurement, especially in applications with high input …
(ADC) mainly used for DC measurement, especially in applications with high input …
[PDF][PDF] A/D-converter performance evolution
BE Jonsson - Converter Passion, 2012 - converterpassion.wordpress.com
This work analyzes the performance evolution over time for monolithic A/D-Converter (ADC)
implementations reported in scientific publications. The work is based on an exhaustive …
implementations reported in scientific publications. The work is based on an exhaustive …
A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs
D Li, C Fei, Q Zhang, Y Li, Y Yang - Journal of Circuits, Systems and …, 2020 - World Scientific
A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for
20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each …
20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each …
A 47.5 MHz BW 4.7 mW 67dB SNDR ringamp based discrete-time delta sigma ADC
This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring
amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3 rd …
amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3 rd …
A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling
A discrete-time, switched-capacitor, MASH 2–2 4 th order ΣΔ modulator, clocked with
frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses …
frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses …
Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
IFCN de Brito - 2023 - search.proquest.com
In modern electronics systems there has been a great push to have a constant size re-
duction of Complementary Metal-Oxide-Semiconductor (CMOS) technologies which can …
duction of Complementary Metal-Oxide-Semiconductor (CMOS) technologies which can …