Study and analysis of advanced 3D multi-gate junctionless transistors
As the IC technology is evolving very rapidly, the feature size of the device has been
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
Performance evaluation of GAA nanosheet FET with varied geometrical and process parameters
NA Kumari, P Prithvi - Silicon, 2022 - Springer
Abstract Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in
sub-7-nm technology. This paper provides insights into the variations of DC FOMs for …
sub-7-nm technology. This paper provides insights into the variations of DC FOMs for …
Epoxy resin/hollow glass microspheres composite materials with low dielectric constant and excellent mechanical performance
X Zhang, M Liu, Y Chen, J He, X Wang… - Journal of Applied …, 2022 - Wiley Online Library
The materials with low dielectric constant and low dielectric loss are vital for high integration
degree of the circuit board. Although many polymers like epoxy resin exhibit excellent …
degree of the circuit board. Although many polymers like epoxy resin exhibit excellent …
Circuit level analysis of a dual material graded channel (DMGC) cylindrical gate all around (CGAA) FET at nanoscale regime
PK Mudidhe, BR Nistala - ECS Journal of Solid State Science and …, 2023 - iopscience.iop.org
Gate-all around (GAA) device is one of the cutting-edge technologies in the present
semiconductor era owing to enhanced gate controllability and scalability at the nanoscale …
semiconductor era owing to enhanced gate controllability and scalability at the nanoscale …
Analog/RF performance analysis of channel engineered high-k gate-stack based junctionless trigate-FinFET
In this paper, the effect of channel parameters like channel thickness (T Si) and channel
length (L g) on the analog/RF performance of high-K gate-stack based junctionless Trigate …
length (L g) on the analog/RF performance of high-K gate-stack based junctionless Trigate …
Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell
The increasing demand of portable gadgets for emerging VLSI applications call for the low
power 6 T static random-access memory (SRAM) cell design. In this work, a 6 T SRAM cell …
power 6 T static random-access memory (SRAM) cell design. In this work, a 6 T SRAM cell …
Optimization of Device Dimensions of High-k Gate Dielectric Based DG-TFET for Improved Analog/RF Performance
The optimization of device dimensions along with high-k gate dielectric is investigated in this
work for improving RF/analog performance of double gate (DG) TFET device. Through …
work for improving RF/analog performance of double gate (DG) TFET device. Through …
Analytical model of double gate stacked oxide junctionless transistor considering source/drain depletion effects for CMOS low power applications
This paper proposes a 2-D analytical model developed for Double Gate Junctionless
Transistor with a SiO 2/HfO 2 stacked oxide structure. The model is solved by Poisson's …
Transistor with a SiO 2/HfO 2 stacked oxide structure. The model is solved by Poisson's …
Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective
This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …
Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance
This paper for the first time investigates the effect of temperature variation on analog/RF
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …