Two double-node-upset-hardened flip-flop designs for high-performance applications
The continuous advancement of complementary metal-oxide-semiconductor technologies
makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as …
makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as …
[HTML][HTML] Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era
This paper discusses principles and techniques to evaluate processors for dependable
computing in space applications. The focus is on soft errors, which dominate the failure rate …
computing in space applications. The focus is on soft errors, which dominate the failure rate …
Ionizing Radiation Effectsin Electronics
M Bagatin, S Gerardin - 2016 - api.taylorfrancis.com
There is an invisible enemy that constantly threatens the operation of electronics: ionizing
radiation. From sea level to outer space, ionizing radiation is virtually everywhere. At sea …
radiation. From sea level to outer space, ionizing radiation is virtually everywhere. At sea …
Characterizing SRAM and FF soft error rates with measurement and simulation
M Hashimoto, K Kobayashi, J Furuta, SI Abe… - Integration, 2019 - Elsevier
Soft error originating from cosmic ray is a serious concern for reliability demanding
applications, such as autonomous driving, supercomputer, and public transportation system …
applications, such as autonomous driving, supercomputer, and public transportation system …
Novel double-node-upset-tolerant memory cell designs through radiation-hardening-by-design and layout
A Yan, Z Wu, J Guo, J Song… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper presents two novel memory cell designs that can completely tolerate double-
node upsets. First, a layout dependent cell is proposed. Since the cell has many redundant …
node upsets. First, a layout dependent cell is proposed. Since the cell has many redundant …
Layout-based modeling and mitigation of multiple event transients
Radiation-induced multiple event transients (METs) are expected to become more frequent
than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a …
than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a …
A layout-based approach for multiple event transient analysis
With the emerging nanoscale CMOS technology, Multiple Event Transients (METs)
originated from radiation strikes are expected to become more frequent than Single Event …
originated from radiation strikes are expected to become more frequent than Single Event …
DAD-FF: Hardening designs by delay-adjustable D-flip-flop for soft-error-rate reduction
DYW Lin, CHP Wen - IEEE Transactions on Very Large Scale …, 2020 - ieeexplore.ieee.org
For the safety-critical applications such as biomedical and automobile electronics, the
system failure induced by soft errors becomes a major issue of reliability. However, most of …
system failure induced by soft errors becomes a major issue of reliability. However, most of …
Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches
X Hui, Z Yun - IEICE Electronics Express, 2015 - jstage.jst.go.jp
In this paper, we propose a novel hardened latch to mitigate the SEU. The combination of
the circuit structure and layout placement is adopted to enhance the multiple nodes upset …
the circuit structure and layout placement is adopted to enhance the multiple nodes upset …
Impact of cell distance and well-contact density on neutron-induced multiple cell upsets
J Furuta, K Kobayashi, H Onodera - IEICE Transactions on …, 2015 - search.ieice.org
We measure neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs)
on Flip-Flops (FFs) in a 65-nm bulk CMOS process in order to evaluate dependence of …
on Flip-Flops (FFs) in a 65-nm bulk CMOS process in order to evaluate dependence of …