A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …

A digital PLL (DPLL) with a time-to-digital converter (TDC) embedded within a digitally
controlled oscillator (DCO) has been implemented in 65 nm CMOS occupying an active area …

A highly-digital clock multiplication architecture that achieves excellent jitter and mitigates
supply noise is presented. The proposed architecture utilizes a calibration-free digital …

Phase noise performance of ring oscillator based digital fractional-N phase-locked loops
(FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously …

This paper presents an all-digital PLL (ADPLL) in which all functional blocks have been
synthesized from standard digital cells and automatically placed and routed (P&R). A …

This paper presents an all-digital impulse radio ultra-wideband (IR-UWB) transmitter. All
functional blocks in the transmitter are implemented with digital standard cells and …

This paper introduces a novel architecture of digital PLL. The goal of this architecture is to
reach low jitter, fractional operation, and FSK modulation capability with low architecture …

A 0.3–1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller
(ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The …

This article presents a fractional-digital multiplying delay-locked loop (MDLL) that uses a
digital-to-time converter (DTC) for controlling the reference injection timing to support the …

This article presents a fractional-digital multiplying delay-locked loop (MDLL) that employs a
digital-to-time converter (DTC) to control the reference injection for the fractional-operation …