Security primitives for memoryless IoT devices based on Physical Unclonable Functions and True Random Number Generators

K Gołofit - Scientific Reports, 2024 - nature.com
The article describes various security primitives for significantly resource-constrained
devices, such as sensors or sensor networks, IoT devices, wearables, etc.—ie, devices …

Riding the waves towards generic single-cycle masking in hardware

R Nagpal, B Gigerl, R Primas, S Mangard - Cryptology ePrint Archive, 2022 - eprint.iacr.org
Research on the design of masked cryptographic hardware circuits in the past has mostly
focused on reducing area and randomness requirements. However, many embedded …

Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes

MT Moreira, RA Guazzelli… - 2012 25th Symposium …, 2012 - ieeexplore.ieee.org
The scaling of microelectronic technologies brings new challenges to the design of complex
SoCs. For example, fully synchronous SoCs may soon become unfeasible to build …

Contributions to efficiency and robustness of quasi delay-insensitive circuits

FF Huemer - 2022 - repositum.tuwien.at
In the field of digital integrated circuits asynchronous and especially quasi delay-insensitive
(QDI) designs are known to have a high robustness against process, voltage and …

DICE-based Muller C-elements for soft error tolerant asynchronous ICs

IA Danilov, MS Gorbunov, AI Shnaider… - 2016 16th European …, 2016 - ieeexplore.ieee.org
Muller C-element is one of the main parts of an asynchronous circuit. Being sequential by its
nature, it is vulnerable to single event upsets (SEU). We propose three 65 nm CMOS circuit …

On board electronic devices safety provided by DICE-based Muller C-elements

IA Danilov, MS Gorbunov, AI Shnaider, AO Balbekov… - Acta Astronautica, 2018 - Elsevier
Abstract Space radiation interacting with electronic components of on-board computing or
navigation unit can bring to it's malfunction. Using error tolerant electronic components is a …

Automatic layout synthesis with ASTRAN applied to asynchronous cells

A Ziesemer, R Reis, MT Moreira… - 2014 IEEE 5th Latin …, 2014 - ieeexplore.ieee.org
This work presents ASTRAN, a tool for automatic layout generation of cell libraries, and the
use of this tool in the production of a cell library for asynchronous logic components called …

A practical framework for specification, verification, and design of self-timed pipelines

J Simatic, A Cherkaoui, F Bertrand… - 2017 23rd IEEE …, 2017 - ieeexplore.ieee.org
Asynchronous circuits are interesting alternatives for implementing ultra-low power systems
but they are more challenging to design. This work provides methods for designers to …

Design of NCL gates with the ASCEnD flow

MT Moreira, CHM Oliveira, RC Porto… - 2013 IEEE 4th Latin …, 2013 - ieeexplore.ieee.org
Silicon technologies advances brought the possibility of integrating billions of transistors in a
die. However, as transistors get smaller, some of the aspects that were negligible in previous …

Lichen: Automated electrical characterization of asynchronous standard cell libraries

MT Moreira, CHM Oliveira… - … Conference on Digital …, 2013 - ieeexplore.ieee.org
Semi-custom design flows are a key factor for the rapid growth of integrated circuits and
systems. They lower design complexity through the use of pre-designed and pre …