[PDF][PDF] 计算体系架构研究综述与思考

高彦钊, 邬江兴, 刘勤让, 沈剑良, 宋克, 张帆 - Sci Sin, 2022 - images.ptausercontent.com
摘要随着摩尔定律(Moore's law) 与迪纳德(Dennard) 缩放定律逐步走向终结,
依靠集成电路制程工艺的进步提升计算系统性能与效能越来越困难, 计算体系架构的演进成为了 …

A soft risc-v processor ip with high-performance and low-resource consumption for fpga

T Zheng, G Cai, Z Huang - 2022 IEEE International Symposium …, 2022 - ieeexplore.ieee.org
Compared with hardcore processors, adding softcore processors can help FPGA to improve
reliability. Many existing soft processors only aim at minimizing FPGA resources …

Testing a RISCV-like architecture with an HDL-based virtual tester

N Nosrati, K Basharkhah, HT Asl… - … on Design & …, 2021 - ieeexplore.ieee.org
This paper is on a RISCV-like processor and developing a virtual tester for it. We define a
Virtual Tester as a testbench in an HDL that performs test functions as an automatic test …

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors

MA Islam, H Miyazaki, K Kise - arXiv preprint arXiv:2010.16171, 2020 - arxiv.org
RISC-V, an open instruction set architecture, is getting the attention of soft processor
developers. Implementing only a basic 32-bit integer instruction set of RISC-V, which is …

An Efficient Resource Shared RISC-V Multicore Architecture

MA Islam, K Kise - IEICE TRANSACTIONS on Information and …, 2022 - search.ieice.org
For the increasing demands of computation, heterogeneous multicore architecture is
believed to be a promising solution to fulfill the edge computational requirement. In FPGAs …

RVCoreP-32IC: An optimized RISC-V soft processor supporting the compressed instructions

T Kanamori, K Kise - … Multicore/Many-core Systems-on-Chip …, 2021 - ieeexplore.ieee.org
The compressed instructions extension in RISC-V reduces the program size. However, it
needs a complicated logic for the instruction fetch unit and has an impact on performance. In …

An optimized RISC-V processor with five stage pipelining using Tournament Branch Predictor for efficient performance

A Choudhury, SV Siddamal… - … on Distributed Computing …, 2022 - ieeexplore.ieee.org
A RISC-V is an open-source standard computer architecture that uses reduced instruction
sets and provides researchers and developers to learn, develop and contribute to the …

RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor

T Kanamori, T Odan, K Hirohata… - IEICE TRANSACTIONS on …, 2022 - search.ieice.org
Deep Neural Network (DNN) is widely used for computer vision tasks, such as image
classification, object detection, and segmentation. DNN accelerator on FPGA and especially …

Efficient resource shared RISC-V multicore processor

MA Islam, K Kise - 2021 IEEE 14th International Symposium on …, 2021 - ieeexplore.ieee.org
Edge computing pushes the computational loads from the cloud to embedded devices,
where data would be processed near the data source. Heterogeneous multicore architecture …

Разработка RISC-V процессора для применения в системах на кристалле

СА Корнев, ВВ Андреев - Электронный журнал: наука, техника и …, 2021 - elibrary.ru
В работе описана конструкция конфигурируемого процессорного ядра на основе
архитектуры RISC-V. Разработанное процессорное ядро основано на базовом наборе …