The disclosed embodiments are directed to systems and method for floorplanning an
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …

US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …

US9099526B2 - Integrated circuit device and structure - Google Patents US9099526B2 -
Integrated circuit device and structure - Google Patents Integrated circuit device and structure …

H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …

A device, including: a first structure including first memory cells, the first memory cells
including first transistors; and a second structure including second memory cells, the second …

A method for processing a 3D semiconductor device, the method including: providing a
wafer including a plurality of first dies, the plurality of first dies including a first transistor layer …

H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …

A multilevel semiconductor device including: a first level including a first array of first memory
cells and first control line; a second level including a second array of second memory cells …

H01L23/522—Arrangements for conducting electric current within the device in operation
from one component to another, ie interconnections, eg wires, lead frames including …

A 3D memory device, the device including: a first single crystal layer including memory
peripheral circuits; a first memory layer including a first junction-less transistor; a second …