An in-memory multiply and accumulate circuit includes a memory array, such as a NOR flash
array, storing weight values W i, n. A row decoder is coupled to the set of word lines, and …

G11C11/41—Digital stores characterised by the use of particular electric or magnetic
storage elements; Storage elements therefor using electric elements using semiconductor …

2020-04-27 Assigned to CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
reassignment CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. ASSIGNMENT …

A time-multiplexed group of MAC circuits for a machine learning application is provided in
which at least one MAC circuit in the time-multiplexed group also functions as a capacitive …

Conventional SRAM sense-amplifiers are replaced by small-footprint keeper circuits that
enable single-ended SRAM readout without bitline precharge, simplifying and relaxing the …

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for
storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of …

2021-02-18 Assigned to QUALCOMM INCORPORATED reassignment QUALCOMM
INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

An in-memory computation device including a memory array, pxq analog to digital
converters (ADCs) and a ladder adder is provided. The memory array is divided into pxq …

A charge sharing scheme is used to mitigate the variations in cell currents in order to
achieve higher accuracy for CIM computing. In some embodiments, a capacitor is …

This application relates to methods and apparatus for computing, especially to circuitry for
performing computing, at least partly, in the analogue domain. The circuitry (200) comprises …